Search Result "low power VLSI."


Research Article

CNFET Based Low Power Full Adder Circuit for VLSI Applications

Journal: Nanoscience & Nanotechnology-Asia
Volume: 10 Issue: 3 Year: 2020 Page: 286-291
Author(s): Inamul Hussain,Saurabh Chaudhury

A Comparative Analysis and Ideas to Reduce Various Leakage Power in Modern VLSI

Ebook: Nanoscale Field Effect Transistors: Emerging Applications
Volume: 1 Year: 2023
Author(s):
Doi: 10.2174/9789815165647123010012

Review Article

VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Journal: Recent Patents on Computer Science
Volume: 9 Issue: 3 Year: 2016 Page: 216-221
Author(s): Abdul Kareem,Vardhana M.,Praveen Kumar

Mini-Review Article

A Survey on Low Power Design Approaches in Nanoscale Regime

Journal: Micro and Nanosystems
Volume: 13 Issue: 2 Year: 2021 Page: 129-145
Author(s): Vijay Kumar Sharma

Editorial free to download

Recent Trends in Low-power VLSI and Embedded System

Journal: Recent Advances in Electrical & Electronic Engineering
Volume: 14 Issue: 4 Year: 2021 Page: 375-376
Author(s): Abdul Quaiyum Ansari,Mohammad Ayoub Khan

Review Article

Comprehensive Study of Low-Power SRAM Design Topologies

Journal: Recent Advances in Electrical & Electronic Engineering
Volume: 17 Issue: 9 Year: 2024 Page: 849-858
Author(s): Shailendra Kumar Tripathi,Sushanta Kumar Mandal

Review Article

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Journal: Current Nanoscience
Volume: 20 Issue: 3 Year: 2024 Page: 298-313
Author(s): Vijay Kumar Sharma

Review Article

Design and Implementation of CCTA for Low Power Applications: A Review

Journal: Recent Advances in Electrical & Electronic Engineering
Volume: 14 Issue: 4 Year: 2021 Page: 406-414
Author(s): Shailendra Bisariya,Neelofer Afzal

Low Voltage and Low Power Pulse Flip-Flops in Nanometer CMOS Processes

Journal: Current Nanoscience
Volume: 8 Issue: 1 Year: 2012 Page: 102-107
Author(s): Jianping Hu, Xiaoying Yu

Low Energy, Low Latency and High Speed Array Divider Circuit Using a Shannon Theorem Based Adder Cell

Journal: Recent Patents on Nanotechnology
Volume: 3 Issue: 1 Year: 2009 Page: 61-72
Author(s): Chinnaiyan Senthilpari, Krishnamoorthy Diwakar, Ajay K. Singh

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