Comprehensive Study of Low-Power SRAM Design Topologies

Title:Comprehensive Study of Low-Power SRAM Design Topologies

Volume: 16

Author(s): Anandita Srivastava, Shailendra Kumar Tripathi*, Usha Tiwari and Sushanta Kumar Mandal

Affiliation:

• Department of ECE, K.L. University, Guntur, India

Abstract: The need for low power in portable and smart devices is the demand to be fulfilled for sustaining the semiconductor industry. Static Random Access Memory (SRAM) is the main part of the core design in chips. It is important to reduce the leakage power consumption during the steady mode of the device for the long run of the battery. This article is about the study of different modules using pre-existing low power. Application of different methods other than lowering the supply voltage leads to an increment in the number of transistors in conventional 6T (six transistor) SRAM cells like 7T to 14T. Power gating and the Multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is the most relevant method. Hybrid low power techniques are in high demand because it shows better results than using individual techniques. However, the biggest challenge is to maintain the area and delay as well. FinFET came into the scenario to overcome the leakage power and short channel effect due to scaling in CMOS. Comparative study analysis shows that FinFET decreases the overall power and delay even when the number of transistors increases. A comparison was done between 6T, 8T, and 10T using FinFET and CMOS in a paper, and concluded that FinFET shows 77.792% improved write power.

Cite this article as:

Srivastava Anandita, Tripathi Shailendra Kumar*, Tiwari Usha and Mandal Sushanta Kumar, Comprehensive Study of Low-Power SRAM Design Topologies, Recent Advances in Electrical & Electronic Engineering 2023; 16 () . https://dx.doi.org/10.2174/0123520965275861231027060817