Login Register Cart 0
Generic placeholder image

Current Nanoscience

Editor-in-Chief

ISSN (Print): 1573-4137
ISSN (Online): 1875-6786

Back
Journal Home About Journal Editorial Board Journal Insight Current Issue Volumes/Issues
Subscribe
Review Article

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Author(s): Kajal and Vijay Kumar Sharma*

Volume 20, Issue 3, 2024

Published on: 12 October, 2023

Page: [298 - 313] Pages: 16

DOI: 10.2174/0115734137252023230919054547

Price: $65

conference banner
Abstract

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices.

Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI.

Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies.

Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

« Previous Next »
Graphical Abstract

[1]
Djezzar, B.; Benabdelmoumene, A.; Zatout, B.; Messaoud, D.; Chenouf, A.; Tahi, H. Recovery investigation of NBTI-induced traps in n-MOSFET devices. Microelectron. Reliab., 2020, 110(113703), 113703.
[http://dx.doi.org/10.1016/j.microrel.2020.113703]
[2]
Mahapatra, S.; Parihar, N. A review of NBTI mechanisms and models. Microelectron. Reliab., 2018, 81, 127-135.
[http://dx.doi.org/10.1016/j.microrel.2017.12.027]
[3]
Tan, S.X-D.; Amrouch, H.; Kim, T.; Sun, Z.; Cook, C.; Henkel, J. Recent advances in EM and BTI induced reliability modeling, analysis and optimization. Integration, 2018, 60, 132-152.
[http://dx.doi.org/10.1016/j.vlsi.2017.08.009]
[4]
Chen, X.; Wang, Y.; Yang, H.; Xie, Y.; Cao, Y. Assessment of circuit optimization techniques under NBTI. IEEE Des. Test, 2013, 30(6), 40-49.
[http://dx.doi.org/10.1109/mdat.2013.2266651]
[5]
Jeppson, K.O.; Svensson, C.M. Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices. J. Appl. Phys., 1977, 48(5), 2004-2014.
[http://dx.doi.org/10.1063/1.323909]
[6]
Alam, M.A. A critical examination of the mechanics of dynamic NBTI for PMOSFETs. IEEE International Electron Devices Meeting 2003; Washington, DC, USA, 2003, p. 14.4.1-14.4.4.
[7]
Chakravarthi, S.; Krishnan, A.; Reddy, V.; Machala, C.F.; Krishnan, S. A comprehensive framework for predictive modeling of negative bias temperature instability. 2004 IEEE International Reliability Physics Symposium Proceedings, Phoenix, AZ, USA2004, pp. 273-282.
[8]
Islam, A.E.; Kufluoglu, H.; Varghese, D.; Mahapatra, S.; Alam, M.A. Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation. IEEE Trans. Electron Dev., 2007, 54(9), 2143-2154.
[http://dx.doi.org/10.1109/ted.2007.902883]
[9]
Kimizuka, N.; Yamaguchi, K.; Imai, K.; Iizuka, T.; Liu, C.T.; Keller, R.C. NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-μm gate CMOS generation. 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat.No.00CH37104); Honolulu, HI, USA, 2000, p. 92-93.
[10]
Mahapatra, S.; Goel, N.; Desai, S.; Gupta, S.; Jose, B.; Mukhopadhyay, S. A comparative study of different physics-based NBTI models. IEEE Trans. Electron Dev., 2013, 60(3), 901-916.
[http://dx.doi.org/10.1109/ted.2013.2238237]
[11]
Schroder, D.K. Negative bias temperature instability: What do we understand? Microelectron. Reliab., 2007, 47(6), 841-852.
[http://dx.doi.org/10.1016/j.microrel.2006.10.006]
[12]
Kajal, S. V.K. An investigation for the Negative-Bias Temperature Instability aware CMOS logic. Micro Nanosyst., 2021, 13(4), 405-417.
[http://dx.doi.org/10.2174/1876402913666210125144339]
[13]
Yu, L.; Ren, J.; Lu, X.; Wang, X. NBTI and HCI aging prediction and reliability screening during production test. IEEE Trans Comput-aided Des Integr Circuits Syst., 2020, 39(10), 3000-3011.
[http://dx.doi.org/10.1109/tcad.2019.2961329]
[14]
Kaffashian, H.M.; Lotfi, R.; Mafinezhad, K.; Mahmoodi, H. Impact of NBTI on performance of domino logic circuits in nano-scale CMOS. Microelectronics J., 2011, 42(12), 1327-1334.
[http://dx.doi.org/10.1016/j.mejo.2011.09.009]
[15]
Roy, S.; Pan, D.Z. Reliability aware gate sizing combating NBTI and oxide breakdown. 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems; Mumbai, India, 2014, p. 38-43.
[16]
Kaczer, B.; Arkbipov, V.; Degraeve, R.; Collaert, N.; Groeseneken, G.; Goodwin, M. Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification. 2005 IEEE International Reliability Physics Symposium, Proceedings. 43rd Annual; San Jose, CA, USA, 2005, p. 381-387.
[17]
Mitani, Y.; Nagamine, M.; Satake, H.; Toriumi, A. NBTI mechanism in ultra-thin gate dielectric - nitrogen-originated mechanism in SiON. Digest. International Electron Devices Meeting, San Francisco, CA, USA2002, pp. 509-512.
[18]
Grasser, T.; Waltl, M.; Rzepa, G.; Goes, W.; Wimmer, Y.; El-Sayed, A-M. The “permanent” component of NBTI revisited: Saturation, degradation-reversal, and annealing. 2016 IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA 2016.
[19]
Stathis, J.H. The physics of NBTI: What do we really know? 2018 IEEE International Reliability Physics Symposium (IRPS), 2018, pp. 2A-14.
[20]
Alam, M.A.; Mahapatra, S. A comprehensive model of PMOS NBTI degradation. Microelectron. Reliab., 2005, 45(1), 71-81.
[http://dx.doi.org/10.1016/j.microrel.2004.03.019]
[21]
Alam, M.A.; Kufluoglu, H.; Varghese, D.; Mahapatra, S. A comprehensive model for PMOS NBTI degradation: Recent progress. Microelectron. Reliab., 2007, 47(6), 853-862.
[http://dx.doi.org/10.1016/j.microrel.2006.10.012]
[22]
Chaudhary, A.; Mahapatra, S. A physical and SPICE mobility degradation analysis for NBTI. IEEE Trans. Electron Dev., 2013, 60(7), 2096-2103.
[http://dx.doi.org/10.1109/ted.2013.2259493]
[23]
Parihar, N.; Goel, N.; Mukhopadhyay, S.; Mahapatra, S. BTI analysis tool—modeling of NBTI DC, AC stress and recovery time kinetics, nitrogen impact, and EOL estimation. IEEE Trans. Electron Dev., 2018, 65(2), 392-403.
[http://dx.doi.org/10.1109/ted.2017.2780083]
[24]
Choudhury, N.; Parihar, N.; Goel, N.; Thirunavukkarasu, A.; Mahapatra, S. Modeling of DC-AC NBTI stress-recovery time kinetics in P-channel planar bulk and FDSOI MOSFETs and FinFETs. IEEE J. Electron Devices Soc., 2020, 8, 1281-1288.
[http://dx.doi.org/10.1109/JEDS.2020.3023803]
[25]
Chaudhary, A.; Fernandez, B.; Parihar, N.; Mahapatra, S. Consistency of the two component composite modeling framework for NBTI in large and small area p-MOSFETs. IEEE Trans. Electron Dev., 2017, 64(1), 256-263.
[http://dx.doi.org/10.1109/ted.2016.2630311]
[26]
Atzeni, L.; Manzini, S. Effect of body bias on NBTI of p-MOSFETs. IEEE Trans. Device Mater. Reliab., 2017, 17(2), 399-403.
[http://dx.doi.org/10.1109/tdmr.2017.2694864]
[27]
Tahi, H.; Tahanout, C.; Boubaaya, M.; Djezzar, B.; Merah, S.M.; Nadji, B. Experimental investigation of NBTI degradation in power VDMOS transistors under low magnetic field. IEEE Trans. Device Mater. Reliab., 2017, 17(1), 99-105.
[http://dx.doi.org/10.1109/tdmr.2017.2666260]
[28]
Gao, R.; Ji, Z.; Manut, A.B.; Zhang, J.F.; Franco, J.; Hatta, W.M.S. NBTI-generated defects in nanoscaled devices: Fast characterization methodology and modeling. IEEE Trans. Electron Dev., 2017, 64(10), 4011-4017.
[http://dx.doi.org/10.1109/ted.2017.2742700]
[29]
Prakash, O.; Beniwal, S.; Maheshwaram, S.; Bulusu, A.; Singh, N.; Manhas, S.K. Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits. IEEE Trans. Device Mater. Reliab., 2017, 17(2), 404-413.
[http://dx.doi.org/10.1109/tdmr.2017.2694709]
[30]
Waltl, M.; Rzepa, G.; Grill, A.; Goes, W.; Franco, J.; Kaczer, B. Superior NBTI in high- k SiGe transistors–part I: Experimental. IEEE Trans. Electron Dev., 2017, 64(5), 2092-2098.
[http://dx.doi.org/10.1109/ted.2017.2686086]
[31]
Waltl, M.; Rzepa, G.; Grill, A.; Goes, W.; Franco, J.; Kaczer, B. Superior NBTI in high-k SiGe transistors–part II: Theory. IEEE Trans. Electron Dev., 2017, 64(5), 2099-2105.
[http://dx.doi.org/10.1109/ted.2017.2686454]
[32]
Yu, X.; Cheng, R.; Liu, W.; Qu, Y.; Han, J.; Chen, B. A fast Vth measurement (FVM) technique for NBTI behavior characterization. IEEE Electron Device Lett., 2018, 39(2), 172-175.
[http://dx.doi.org/10.1109/led.2017.2781243]
[33]
Yu, X.; Lu, J.; Liu, W.; Qu, Y.; Zhao, Y. Ultra-fast (ns-scale) characterization of NBTI behaviors in Si pFinFETs. IEEE J. Electron Devices Soc., 2020, 8, 577-583.
[http://dx.doi.org/10.1109/jeds.2020.2989413]
[34]
Roelke, A.; Stan, M.R. Controlling the reliability of SRAM PUFs with directed NBTI aging and recovery. IEEE Trans. Very Large Scale Integr. (VLSI). Syst., 2018, 26(10), 2016-2026.
[http://dx.doi.org/10.1109/tvlsi.2018.2836154]
[35]
Yang, T.; Kim, D.; Li, J.; Kinget, P.R.; Seok, M. In situ and in-field technique for monitoring and decelerating NBTI in 6T-SRAM register files. IEEE transactions on very large scale integration (VLSI). Systems., 2018, 26(11), 2241-2253.
[http://dx.doi.org/10.1109/TVLSI.2018.2856528]
[36]
Li, X.; Qing, J.; Sun, Y.; Zeng, Y.; Shi, Y.; Wang, Y. Linear and resolution adjusted on-chip aging detection of NBTI degradation. IEEE Trans. Device Mater. Reliab., 2018, 18(3), 383-390.
[http://dx.doi.org/10.1109/tdmr.2018.2847322]
[37]
Mishra, S.; Parihar, N. NBTI-related variability impact on 14-nm node FinFET SRAM performance and static power: Correlation to time zero fluctuations. IEEE Trans. Electron Dev., 2018, 65(11), 4846-4853.
[http://dx.doi.org/10.1109/ted.2018.2869669]
[38]
Tiwari, R.; Parihar, N.; Thakor, K.; Wong, H.Y.; Motzny, S.; Choi, M.A. 3-D TCAD framework for NBTI—part I: Implementation details and FinFET channel material impact. IEEE Trans. Electron Dev., 2019, 66(5), 2086-2092.
[http://dx.doi.org/10.1109/ted.2019.2906339]
[39]
Tiwari, R.; Parihar, N.; Thakor, K.; Wong, H.Y.; Motzny, S.; Choi, M.A. 3-D TCAD framework for NBTI, part-II: Impact of mechanical strain, quantum effects, and FinFET dimension scaling. IEEE Trans. Electron Dev., 2019, 66(5), 2093-2099.
[http://dx.doi.org/10.1109/ted.2019.2906293]
[40]
Thirunavukkarasu, A.; Amrouch, H.; Joe, J.; Goel, N.; Parihar, N.; Mishra, S. Device to circuit framework for activity-dependent NBTI aging in digital circuits. IEEE Trans. Electron Dev., 2019, 66(1), 316-323.
[http://dx.doi.org/10.1109/ted.2018.2882229]
[41]
Sharma, U.; Parihar, N.; Mahapatra, S. Modeling of HCD kinetics for full VG/VD span in the presence of NBTI, electron trapping, and self heating in RMG SiGe p-FinFETs. IEEE Trans. Electron Dev., 2019, 66(6), 2502-2508.
[http://dx.doi.org/10.1109/ted.2019.2911335]
[42]
Mahapatra, S.; Parihar, N. Modeling of NBTI using BAT framework: DC-AC stress-recovery kinetics, material, and process dependence. IEEE Trans. Device Mater. Reliab., 2020, 20(1), 4-23.
[http://dx.doi.org/10.1109/tdmr.2020.2967696]
[43]
Choudhury, N.; Mahapatra, S. A method to isolate intrinsic HCD and NBTI contributions under self heating during varying VG/VD stress in GAA nanosheet PFETs. IEEE Trans. Electron Dev., 2022, 69(7), 3535-3541.
[http://dx.doi.org/10.1109/ted.2022.3172055]
[44]
Zhou, L.; Liu, Q.; Yang, H.; Ji, Z.; Xu, H.; Tang, B. Insights into the effect of TiN thickness scaling on DC and AC NBTI characteristics in replacement metal gate pMOSFETs. IEEE Trans. Device Mater. Reliab., 2020, 20(3), 498-505.
[http://dx.doi.org/10.1109/tdmr.2020.2997811]
[45]
Zhou, L.; Wang, G.; Yin, X.; Ji, Z.; Liu, Q.; Xu, H. Comparative study on NBTI kinetics in Si p-FinFETs with B2H6-based and SiH4-based atomic layer deposition tungsten (ALD W) filling metal. Microelectron. Reliab., 2020, 107(113627), 113627.
[http://dx.doi.org/10.1016/j.microrel.2020.113627]
[46]
Ye, B.; Gu, Y.; Xu, H.; Tang, C.; Zhu, H.; Sun, Q. NBTI mitigation by optimized HKMG thermal processing in a FinFET technology. IEEE Trans. Electron Dev., 2022, 69(3), 905-909.
[http://dx.doi.org/10.1109/ted.2021.3139566]
[47]
Liu, C.; Xiao, Z.; Ma, S.; Bi, D.; Hu, Z.; Zhang, Z. Analysis of DC characteristics in PDSOI pMOSFETs under the combined effect of NBTI and TID. IEEE Trans. Nucl. Sci., 2022, 69(5), 1148-1156.
[http://dx.doi.org/10.1109/tns.2021.3138077]
[48]
Chen, X.; Wang, Y.; Cao, Y.; Ma, Y.; Yang, H. Variation-aware supply voltage assignment for simultaneous power and aging optimization. IEEE Trans. Very Large Scale Integr. (VLSI). Syst., 2012, 20(11), 2143-2147.
[http://dx.doi.org/10.1109/tvlsi.2011.2168433]
[49]
Lin, I-C.; Syu, S-M.; Ho, T-Y. NBTI tolerance and leakage reduction using gate sizing. ACM J. Emerg. Technol. Comput. Syst., 2014, 11(1), 1-12.
[http://dx.doi.org/10.1145/2629657]
[50]
Sun, P.; Yang, Z.; Yu, Y.; Li, J.; Peng, X. NBTI and power reduction using an input vector control and supply voltage assignment method. Algorithms, 2017, 10(3), 94.
[http://dx.doi.org/10.3390/a10030094]
[51]
Kaffashian, H.M.; Lotfi, R.; Mafinezhad, K.; Mahmoodi, H. Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS. Microelectron. Reliab., 2012, 52(8), 1655-1659.
[http://dx.doi.org/10.1016/j.microrel.2012.03.012]
[52]
Suvarnamma, A.; Rajashekar, M. NBTI and process variation circuit design using adaptive body biasing. IOSR J VLSI Signal Process., 2014, 4(2), 91-98.
[http://dx.doi.org/10.9790/4200-04239198]
[53]
He, Y.; Du, G.; Yang, Y.; Zhang, G.; Zhang, X.; Wang, Y. Forward-body-bias-enhanced negative bias temperature instability recovery of p-channel metal–oxide–semiconductor field-effect transistors. Jpn. J. Appl. Phys., 2010, 49(4S), 04DC25.
[54]
He, Y. Effect of variable body bias technique on pMOSFET NBTI recovery. Electron. Lett., 2009, 45(18), 956.
[http://dx.doi.org/10.1049/el.2009.0787]
[55]
Bild, D.R.; Dick, R.P.; Bok, G.E. Static NBTI reduction using internal node control. ACM Trans. Des. Autom. Electron. Syst., 2012, 17(4), 1-30.
[http://dx.doi.org/10.1145/2348839.2348849]
[56]
Johannah, J.J.; Korah, R.; Kalavathy, M. Sivanandham. Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI. Microelectronics, 2017, 62, 137-145.
[http://dx.doi.org/10.1016/j.mejo.2017.02.003]
[57]
Sharma, V.K.; Pattanaik, M. A reliable ground bounce noise reduction technique for nanoscale CMOS circuits. Int. J. Electron., 2015, 102(11), 1852-1866.
[http://dx.doi.org/10.1080/00207217.2014.996786]
[58]
Calimera, A.; Macii, E.; Poncino, M. NBTI-aware clustered power gating. ACM Trans. Des. Autom. Electron. Syst., 2010, 16(1), 1-25.
[http://dx.doi.org/10.1145/1870109.1870112]
[59]
Jin, S.; Han, Y. M-IVC: Applying multiple input vectors to co-optimize aging and leakage. Microelectronics, 2012, 43(11), 838-847.
[http://dx.doi.org/10.1016/j.mejo.2012.06.007]
[60]
Butzen, P.F.; Dal Bem, V.; Reis, A.I.; Ribas, R.P. Design of CMOS logic gates with enhanced robustness against aging degradation. Microelectron. Reliab., 2012, 52(9–10), 1822-1826.
[http://dx.doi.org/10.1016/j.microrel.2012.06.092]
[61]
Chun, J.W.; Chen, C.Y.R. Transistor and pin reordering for leakage reduction in CMOS circuits. Microelectronics, 2016, 53, 25-34.
[http://dx.doi.org/10.1016/j.mejo.2016.04.005]
[62]
Sharma, V.K.; Pattanaik, M. Design of low leakage variability aware ONOFIC CMOS standard cell library. J. Circuits Syst. Comput., 2016, 25(11), 1650134.
[http://dx.doi.org/10.1142/s0218126616501346]
[63]
Sharma, V.K. A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime. Aust. J. Electr. Electron. Eng., 2021, 18(4), 217-236.
[http://dx.doi.org/10.1080/1448837x.2021.1966957]
[64]
Sharma, V.K.; Pattanaik, M.; Raj, B. INDEP approach for leakage reduction in nanoscale CMOS circuits. Int. J. Electron., 2015, 102(2), 200-215.
[http://dx.doi.org/10.1080/00207217.2014.896042]
[65]
Sharma, V.K.; Pattanaik, M. VLSI scaling methods and low power CMOS buffer circuit. J. Semicond., 2013, 34(9), 095001.
[http://dx.doi.org/10.1088/1674-4926/34/9/095001]
[66]
Ciou, F-M.; Hsu, J-T.; Chang, T-C.; Lin, C-Y.; Jin, F-Y.; Lin, Y-S. Investigation of HCD- and NBTI-induced ultralow electric field GIDL in 14-nm technology node FinFETs. IEEE Trans. Electron Dev., 2020, 67(7), 2697-2701.
[http://dx.doi.org/10.1109/ted.2020.2992004]
[67]
Khoshavi, N.; Ashraf, R.A.; DeMara, R.F.; Kiamehr, S.; Oboril, F.; Tahoori, M.B. Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods. Integration, 2017, 59, 10-22.
[http://dx.doi.org/10.1016/j.vlsi.2017.03.013]
[68]
Yang, Z.; Yu, Y.; Zhang, C.; Peng, X. NBTI-aware adaptive minimum leakage vector selection using a linear programming approach. Integration, 2016, 53, 126-137.
[http://dx.doi.org/10.1016/j.vlsi.2015.12.009]
[69]
Kajal; Sharma, V.K. A novel low power technique for FinFET domino OR logic. J. Circuits Syst. Comput., 2021, 30(07), 2150117.
[http://dx.doi.org/10.1142/s0218126621501176]
[70]
Kajal; Sharma, V.K. An efficient low power method for FinFET domino OR logic circuit. Microprocess. Microsyst., 2022, 95(104719), 104719.
[http://dx.doi.org/10.1016/j.micpro.2022.104719]
[71]
Rani, L.V.; Latha, M.M. Pass transistor-based pull-up/pull-down insertion technique for leakage power optimization in CMOS VLSI circuits. Circuits Syst. Signal Process., 2016, 35(11), 4139-4152.
[http://dx.doi.org/10.1007/s00034-016-0257-z]
[72]
Parthasarathy, C.R.; Denais, M.; Huard, V.; Ribes, G.; Roy, D.; Guerin, C. Designing in reliability in advanced CMOS technologies. Microelectron. Reliab., 2006, 46(9–11), 1464-1471.
[http://dx.doi.org/10.1016/j.microrel.2006.07.012]
[73]
Chen, Y.; Xie, Y.; Wang, Y.; Takach, A. Minimizing leakage power in aging-bounded high-level synthesis with design time multi- Vth assignment. 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC); Taipei, Taiwan, 2010, p. 689-694.
[74]
Chen, X.; Wang, Y.; Cao, Y.; Ma, Y.; Yang, H. Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design; New York, NY, USA, 2009, p. 39-44.
[75]
Rao, V.G.; Mahmoodi, H. Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology. 2011 IEEE 29th International Conference on Computer Design (ICCD); Amherst, MA, USA, 2011, p. 439-440.
[76]
Kajal; Sharma, V.K. Reliability and PVT simulation of FinFET circuits using cadence virtuoso. 2021 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT); Mysuru, India, 2021, p. 344-349.
[77]
Riaz, A.; Sharma, V.K. A novel low power 4:2 compressor using FinFET devices. Analog Integr. Circuits Signal Process., 2022, 112(1), 127-139.
[http://dx.doi.org/10.1007/s10470-022-01989-1]
[78]
Kajal; Sharma, VK. Design and simulation for NBTI aware logic gates. Wirel. Pers. Commun., 2021, 120(2), 1525-1542.
[http://dx.doi.org/10.1007/s11277-021-08522-z]
[79]
Mahajan, D.; Ruparelia, V. Reliability simulation and analysis of important RF circuits using Cadence relxpert. 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, India2018, pp. 1-6.

Rights & Permissions Print Cite
© 2024 Bentham Science Publishers | Privacy Policy