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ISSN (Print): 2666-2558
ISSN (Online): 2666-2566

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Research Article

A Binary Particle Swarm Optimization for IC Floorplanning

Author(s): Rajendra Bahadur Singh*, Anurag Singh Baghel and Arun Solanki

Volume 13, Issue 1, 2020

Page: [13 - 21] Pages: 9

DOI: 10.2174/2213275911666181030104939

Price: $65

Abstract

Background: In the field of IC physical design, there is a big problem in the IC floorplanning to find the early feedback to estimate the area, wire length, delay, etc. before IC fabrication.

Objective: In this paper, minimization of the area and total wire length on the IC has been done using Binary Particle Swarm Optimization with sequence pair representation.

Methods: Optimization of the IC floorplan works in two phases. In the first phase, the floorplan is constructed by sequence pair representation without any overlapping of the modules on IC floorplan. In the second phase, Binary Particle Swarm Optimization algorithm explores the packing of all modules in floorplan to find better optimal performances i.e. area and wire length.

Results: The results obtained were compared with the solutions derived from other meta-heuristic algorithms, the area is improved maximum up to 10% and the wire length was improved maximum up to 28%.

Conclusion: The Experimental results on Microelectronic Center of North Carolina benchmark circuits show that Binary Particle Swarm Optimization algorithm gives better convergence for the area and wire length optimization than other algorithms.

Keywords: Floorplanning, binary particle swarm optimization, sequence pair, MCNC benchmarks, NP-hard, integrated circuit, horizontal constraint graph, vertical constraint graph.

Graphical Abstract

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