Abstract
Background: Growing progress in the field of nanoelectronics necessitates ever more advanced nanotechnology due to the continued scaling of conventional devices. For the purpose of fabricating current integrated circuits (ICs), Quantum-dot cellular automata (QCA) nanotechnology is the most suitable substitute for complementary metal oxide semiconductor (CMOS) technology. The problem of short-channel secondary effects at the ultra-nanoscale level confronts CMOS technology.
Aims: QCA nanotechnology overcomes the issues of conventional logic circuit design methods due to its numerous advantages. This research work aims to design an energy-efficient, reliable, universal, 3×3, and reversible logic gate for the implementation of various logical and Boolean functions in QCA nanotechnology.
Objective: It is desirable for portable systems to have a small size, extremely low power consumption, and a clock rate in the terahertz. As a result, QCA nanotechnology is an incredible advancement for digital system applications and the design of future systems.
Methods: This research article proposes a novel, ultra-efficient, multi-operative, 3×3 universal reversible gate implemented in QCA nanotechnology using precise QCA cell interaction. The proposed gate is used for the implementation of all the basic logic gates to validate its universality. The implementation of all thirteen standard Boolean functions establishes the proposed gate's multi-operational nature. The energy dissipation analysis of the design has been presented for the varying setups.
Results: The proposed gate is area-efficient because it uses minimum QCA cells. Various logical and Boolean functions are effectively implemented using the proposed gate. The result analysis establishes the minimum energy dissipation of the proposed design and endorses it as an ultra-efficient design.
Conclusion: The QCA cell interaction method demonstrates the best way to design a universal, reversible, and multi-operative gate.
Graphical Abstract
[1]
Kumar, C.; Mishra, A.S.; Sharma, V.K. Leakage power reduction in cmos logic circuits using stack ONOFIC technique. 2018 Second In-ternational Conference on Intelligent Computing and Control Systems (ICICCS), 2018, pp. 1363-1368.
[http://dx.doi.org/10.1109/ICCONS.2018.8662955]
[http://dx.doi.org/10.1109/ICCONS.2018.8662955]
[2]
Sharma, V.K.; Soni, S. Comparison among different CMOS inverter for low leakage at different technologies. Int. J. Appl. Eng. Res., 2010, 1(2), 228.
[3]
Sharma, V.K. A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime. Aust. J. Electr. Electron. Eng., 2021, 18(4), 217-236.
[4]
Mushtaq, U.; Sharma, V.K. Performance analysis for reliable nanoscaled FinFET logic circuits. Analog Integr. Circuits Signal Process., 2021, 107(3), 671-682.
[http://dx.doi.org/10.1007/s10470-020-01765-z]
[http://dx.doi.org/10.1007/s10470-020-01765-z]
[5]
Sharma, V.K. CNTFET circuit-based wide fan-in domino logic for low power applications. J. Circuits Syst. Comput., 2022, 31(2), 2250036.
[http://dx.doi.org/10.1142/S0218126622500360]
[http://dx.doi.org/10.1142/S0218126622500360]
[6]
Kajal; Sharma, V.K. An efficient low power method for FinFET domino OR logic circuit. Microprocess. Microsyst., 2022, 95, 104719.
[http://dx.doi.org/10.1016/j.micpro.2022.104719]
[http://dx.doi.org/10.1016/j.micpro.2022.104719]
[7]
Riyaz, S.; Sharma, V.K. Design of reversible Feynman and double Feynman gates in quantum-dot cellular automata nanotechnology. Circuit World, 2023, 49(1), 28-37.
[http://dx.doi.org/10.1108/CW-08-2020-0199]
[http://dx.doi.org/10.1108/CW-08-2020-0199]
[8]
Riyaz, S.; Naz, S.F.; Sharma, V.K. Multioperative reversible gate design with implementation of 1‐bit full adder and subtractor along with energy dissipation analysis. Int. J. Circuit Theory Appl., 2021, 49(4), 990-1012.
[http://dx.doi.org/10.1002/cta.2886]
[http://dx.doi.org/10.1002/cta.2886]
[9]
Naz, S.F.; Riyaz, S.; Sharma, V.K. A review of QCA nanotechnology as an alternate to CMOS. Curr. Nanosci., 2022, 18(1), 18-30.
[http://dx.doi.org/10.2174/1573413717666210301111822]
[http://dx.doi.org/10.2174/1573413717666210301111822]
[10]
Raina, B.; Verma, C.; Gupta, M.; Sharma, V.K. Binary coded decimal (BCD) seven segment circuit designing using quantum-dot cellular automata (QCA). 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI) 2021, pp. 126-130.
[11]
Sharma, S; Sharma, VK Design of full adder and parity generator based on reversible logic design of full adder and parity generator based on reversible logic. 2021 Emerging Trends in Industry 4.0 (ETI 4.0), 19-21 May 2021Raigarh, India, 2021.
[http://dx.doi.org/10.1109/ETI4.051663.2021.9619268]
[http://dx.doi.org/10.1109/ETI4.051663.2021.9619268]
[12]
Farrelly, T. A review of quantum cellular automata. Quantum, 2020, 4, 368.
[http://dx.doi.org/10.22331/q-2020-11-30-368]
[http://dx.doi.org/10.22331/q-2020-11-30-368]
[13]
Ahmadpour, S.S.; Navimipour, N.J.; Mosleh, M.; Bahar, A.N.; Yalcin, S. A nano-scale n-bit ripple carry adder using an optimized XOR gate and quantum-dots technology with diminished cells and power dissipation. Nano Commun. Netw., 2023, 36, 100442.
[http://dx.doi.org/10.1016/j.nancom.2023.100442]
[http://dx.doi.org/10.1016/j.nancom.2023.100442]
[14]
Sharma, V.K. Single‐bit digital comparator circuit design using quantum‐dot cellular automata nanotechnology. ETRI J., 2023, 45(3), 534-542.
[http://dx.doi.org/10.4218/etrij.2022-0033]
[http://dx.doi.org/10.4218/etrij.2022-0033]
[15]
Kajal; Sharma, V.K. A novel low power technique for FinFET domino OR logic. J. Circuits Syst. Comput., 2021, 30(7), 2150117.
[http://dx.doi.org/10.1142/S0218126621501176]
[http://dx.doi.org/10.1142/S0218126621501176]
[16]
Kajal; Sharma, V.K. Design and simulation for NBTI aware logic gates. Wirel. Pers. Commun., 2021, 120(2), 1525-1542.
[http://dx.doi.org/10.1007/s11277-021-08522-z]
[http://dx.doi.org/10.1007/s11277-021-08522-z]
[17]
Sharma, V.K. Design and simulation of FinFET circuits at different technologies. 2021 6th International Conference on Inventive Computation Technologies (ICICT), 20-22 January 2021Coimbatore, India, 2021.
[18]
Riaz, A.; Sharma, V.K. A novel low power 4: 2 compressor using FinFET devices. Analog Integr. Circuits Signal Process., 2022, 112(1), 127-139.
[http://dx.doi.org/10.1007/s10470-022-01989-1]
[http://dx.doi.org/10.1007/s10470-022-01989-1]
[19]
Sharma, V.K.; Sharma, V.K. Review of the nanoscale FinFET device for the applications in nano-regime. Curr. Nanosci., 2023, 19(5), 651-662.
[http://dx.doi.org/10.2174/1573413719666221206122301]
[http://dx.doi.org/10.2174/1573413719666221206122301]
[20]
Haq, S.U.; Sharma, V.K. Robust logic circuits design using soi shorted-gate FinFETs. Indian J. Pure Appl. Phy., 2023, 61(01), 57-66.
[21]
Sharma, V.K. Parity generators in QCA nanotechnology for nanocommunication systems. Nano Commun. Netw., 2023, 36, 100440.
[http://dx.doi.org/10.1016/j.nancom.2023.100440]
[http://dx.doi.org/10.1016/j.nancom.2023.100440]
[22]
Mishra, R.; Singh, B.K.; Singh, H.; Sharma, V.K. 101 sequence detector using QCA technology. 2023 International Conference on Com-puter Communication and Informatics (ICCCI), 2023, pp. 1-5.
[23]
Srivastava, S.; Yadav, A.; Chitransh, K.; Sharma, V.K. Design of block coding 4B/5B for digital communication using quantum-dot cellu-lar automata technology. 2021 International Conference on Computer Communication and Informatics (ICCCI), 2021, pp. 1-5.
[http://dx.doi.org/10.1109/ICCCI50826.2021.9402573]
[http://dx.doi.org/10.1109/ICCCI50826.2021.9402573]
[24]
Sharma, V.K. Optimal design for digital comparator using QCA nanotechnology with energy estimation. Int. J. Numer. Model., 2021, 34(2), e2822.
[http://dx.doi.org/10.1002/jnm.2822]
[http://dx.doi.org/10.1002/jnm.2822]
[25]
Wang, R.J.; Xu, Y.P.; She, C.; Nasution, M. A new design for programmable logic array based on QCA-based nanotechnology. Optik, 2022, 253, 168581.
[http://dx.doi.org/10.1016/j.ijleo.2022.168581]
[http://dx.doi.org/10.1016/j.ijleo.2022.168581]
[26]
Khan, A.; Arya, R. Design and energy dissipation analysis of simple QCA multiplexer for nanocomputing. J. Supercomput., 2022, 78(6), 8430-8444.
[http://dx.doi.org/10.1007/s11227-021-04191-8]
[http://dx.doi.org/10.1007/s11227-021-04191-8]
[27]
Gassoumi, I.; Touil, L.; Mtibaa, A. Design of efficient binary-coded decimal adder in QCA technology with a regular clocking scheme. Comput. Electr. Eng., 2022, 101, 107999.
[http://dx.doi.org/10.1016/j.compeleceng.2022.107999]
[http://dx.doi.org/10.1016/j.compeleceng.2022.107999]
[28]
Sharma, V.K. Optimal design for 1:2 n demultiplexer using QCA nanotechnology with energy dissipation analysis. Int. J. Numer. Model., 2021, 34(6), e2907.
[http://dx.doi.org/10.1002/jnm.2907]
[http://dx.doi.org/10.1002/jnm.2907]
[29]
Riyaz, S.; Nashit, R.M.; Kumar, S.V. Reversible code converters in QCA nanotechnology. Mater. Today Proc., 2022, 63, 440-446.
[http://dx.doi.org/10.1016/j.matpr.2022.03.446]
[http://dx.doi.org/10.1016/j.matpr.2022.03.446]
[30]
Anjalideep, K.; Kumar, H.; Srivastava, S.; Sharma, V.K. QCAbased single-bit comparator circuit. 2022 3rd International Conference on Smart Electronics and Communication (ICOSEC), 2022, pp. 328-332.
[31]
Enayati, M.; Rezai, A.; Karimi, A. Novel circuit design for content-addressable memory in QCA technology. Photonic Netw. Commun., 2023, 45(2), 79-88.
[http://dx.doi.org/10.1007/s11107-022-00990-y]
[http://dx.doi.org/10.1007/s11107-022-00990-y]
[32]
Laajimi, R.; Touil, L.; Bahar, A.N. A novel efficient coplanar QCA full adder and full subtractor design. Int. J. Electron., 2023, 110(8), 1431-1446.
[http://dx.doi.org/10.1080/00207217.2022.2098386]
[http://dx.doi.org/10.1080/00207217.2022.2098386]
[33]
Srivastava, S.; Chitransh, K.; Sharma, V.K. Block coding 3B/4B for digital communication using quantum-dot cellular automata technology. 2021 3rd International Conference on Signal Processing and Communication (ICPSC), 2021, pp. 335-339.
[34]
Sharma, V.K.; Malik, M.A. Performance analysis of 6T SRAM and ONOFIC cells. Micro Nanosyst., 2022, 14(4), 350-357.
[http://dx.doi.org/10.2174/1876402913666211202114736]
[http://dx.doi.org/10.2174/1876402913666211202114736]
[35]
Akbari-Hasanjani, R.; Sabbaghi-Nadooshan, R. Tree router design using a novel optimal QCA DEMUX. Nano Commun. Netw., 2023, 35, 100439.
[http://dx.doi.org/10.1016/j.nancom.2023.100439]
[http://dx.doi.org/10.1016/j.nancom.2023.100439]
[36]
Yan, A.; Cao, A.; Liu, R.; Li, X. QCA-based designs of majority gates, flip-flops and polar encoders. In: Quantum-Dot Cellular Automata Circuits for Nanocomputing Applications, 1st Ed; CRC Press, 2023.
[37]
Ahmadpour, S.S.; Navimipour, N.J.; Mosleh, M.; Yalcin, S. Nano-design of ultra-efficient reversible block based on quantum-dot cellular automata. Front. Inf. Technol. Electron., 2023, 24(3), 447-456.
[http://dx.doi.org/10.1631/FITEE.2200095]
[http://dx.doi.org/10.1631/FITEE.2200095]
[38]
Sharma, V.K.; Dhillon, A.; Sharma, M. Multi-functional reversible logic gate using QCA nanotechnology. In: 2022 6th International Conference on Trends in Electronics and Informatics; , 2022; pp. 107-111.
[http://dx.doi.org/10.1109/ICOEI53556.2022.9776683]
[http://dx.doi.org/10.1109/ICOEI53556.2022.9776683]
[39]
Fouladinia, F.; Gholami, M. Decimal to excess-3, BCD, and gray code converters with a novel 4-inputs block in QCA. Opt. Quantum Electron., 2023, 55(10), 862.
[http://dx.doi.org/10.1007/s11082-023-05144-6]
[http://dx.doi.org/10.1007/s11082-023-05144-6]
[40]
Huang, X.; Yan, G.; Yang, X. A new design for XOR gate-based reversible double Feynman gate in nano-scale quantum-dots. Optik, 2023, 278, 170647.
[http://dx.doi.org/10.1016/j.ijleo.2023.170647]
[http://dx.doi.org/10.1016/j.ijleo.2023.170647]
[41]
Sharma, V.K. QCA-based reliable fundamental units for multiplexer-demultiplexer and d-flip-flop. Int. J. Nanosci., 2023, 22(1), 2350001.
[http://dx.doi.org/10.1142/S0219581X23500011]
[http://dx.doi.org/10.1142/S0219581X23500011]
[42]
Wu, C.; Zhao, Z.; Liu, Y.; Mohammed, B.O. Quantum-dot cellular automata-based design for three-level nanoscale full-subtractor. Zhongguo Wuli Xuekan, 2023, 84, 240-247.
[http://dx.doi.org/10.1016/j.cjph.2022.10.014]
[http://dx.doi.org/10.1016/j.cjph.2022.10.014]
[43]
Sharma, V.K. Reversible logic gates using quantum dot cellular automata (QCA) nanotechnology. In: AI for Big Data-Based Engineering Applications from Security Perspectives, 1st Ed. CRC Press; , 2023.
[44]
Wang, Y.; Faghani, S. A new efficient nanodesign of composite gate based on quantum dot cellular automata. Nano, 2023, 18(2), 2250103.
[http://dx.doi.org/10.1142/S179329202250103X]
[http://dx.doi.org/10.1142/S179329202250103X]
[45]
Al-Khafaji, H.M.R.; Kalajahi, A.T.; Darbandi, M.; Ghasemi, A.; Mohammed, A.H.; Cifci, M.A. Performance optimization of the nano-scale carry-skip adder based on quantum dots and its application in the upcoming Internet of Things. Optik, 2023, 287, 170976.
[http://dx.doi.org/10.1016/j.ijleo.2023.170976]
[http://dx.doi.org/10.1016/j.ijleo.2023.170976]
[46]
Safaiezadeh, B.; Kettunen, L.; Haghparast, M. Novel high-performance QCA Fredkin gate and designing scalable QCA binary to gray and vice versa. J. Supercomput., 2023, 79(6), 7037-7060.
[http://dx.doi.org/10.1007/s11227-022-04939-w]
[http://dx.doi.org/10.1007/s11227-022-04939-w]
[47]
Sharma, V.K. Single layer adder/subtractor using QCA nanotechnology for nanocomputing operations. ERX, 2022, 4(4), 045002.
[http://dx.doi.org/10.1088/2631-8695/ac9957]
[http://dx.doi.org/10.1088/2631-8695/ac9957]
[48]
Alharbi, M.; Edwards, G.; Stocker, R. Novel ultra-energy-efficient reversible designs of sequential logic quantum-dot cellular automata flip-flop circuits. J. Supercomput., 2023, 79(10), 11530-11557.
[http://dx.doi.org/10.1007/s11227-023-05134-1]
[http://dx.doi.org/10.1007/s11227-023-05134-1]
[49]
Sharma, V.K. Structure for demultiplexer in QCA technology for nanocommunication systems. 2022 International Conference on Electri-cal, Computer, Communications and Mechatronics Engineering (ICECCME), 2022, pp. 1-5.
[http://dx.doi.org/10.1109/ICECCME55909.2022.9987794]
[http://dx.doi.org/10.1109/ICECCME55909.2022.9987794]
[50]
Sharma, V.K. Parity generators for nanocommunication systems using QCA nanotechnology. Period. Polytech. Electr. Eng. Comput. Sci., 2023, 67(2), 229-237.
[http://dx.doi.org/10.3311/PPee.20602]
[http://dx.doi.org/10.3311/PPee.20602]
[51]
Shaik, E.H.; Mannava, B.R.; Shaik, M.S.; Rangaswamy, N. QCA-based pulse/bit sequence detector using low quantum cost d-flip flop. J. Circuits Syst. Comput., 2023, 32(5), 2350082.
[http://dx.doi.org/10.1142/S0218126623500822]
[http://dx.doi.org/10.1142/S0218126623500822]
[52]
Sharma, V.K. Quantum-dot cellular automata (QCA) nanotechnology for next-generation systems. In: Nanoelectronics for Next-Generation Integrated Circuits; CRC Press, 2022; pp. 57-80.
[53]
Rezai, A.; Aliakbari, D.; Karimi, A. Novel multiplexer circuit design in quantum-dot cellular automata technology. Nano Commun. Netw., 2023, 35, 100435.
[http://dx.doi.org/10.1016/j.nancom.2023.100435]
[http://dx.doi.org/10.1016/j.nancom.2023.100435]
[54]
Mohammadi, H.; Navi, K.; Hosseinzadeh, M. An efficient quantum-dot cellular automata full adder based on a new convertible 7-input majority-not gate. J. Inst. Electron. Telecommun. Eng., 2023, 69(1), 558-566.
[http://dx.doi.org/10.1080/03772063.2020.1838338]
[http://dx.doi.org/10.1080/03772063.2020.1838338]
[55]
Singh, P.; Singh, R. A sliced architecture using novel configurable logic modules in quantum dot cellular automata for application of field-programmable gate arrays. J. Supercomput., 2023, 79(4), 4105-4125.
[http://dx.doi.org/10.1007/s11227-022-04812-w]
[http://dx.doi.org/10.1007/s11227-022-04812-w]
[56]
Thapliyal, H.; Ranganathan, N. Reversible logic-based concurrently testable latches for molecular QCA. IEEE Trans. Nanotechnol., 2010, 9(1), 62-69.
[http://dx.doi.org/10.1109/TNANO.2009.2025038]
[http://dx.doi.org/10.1109/TNANO.2009.2025038]
[57]
Sasamal, T.N.; Singh, A.K.; Mohan, A. Efficient design of reversible alu in quantum-dot cellular automata. Optik, 2016, 127(15), 6172-6182.
[http://dx.doi.org/10.1016/j.ijleo.2016.04.086]
[http://dx.doi.org/10.1016/j.ijleo.2016.04.086]
[58]
Roohi, A.; Zand, R.; Angizi, S.; DeMara, R.F. A parity-preserving reversible QCA gate with self-checking cascadable resiliency. IEEE Trans. Emerg. Top. Comput., 2018, 6(4), 450-459.
[http://dx.doi.org/10.1109/TETC.2016.2593634]
[http://dx.doi.org/10.1109/TETC.2016.2593634]
[59]
Bilal, B.; Ahmed, S.; Kakkar, V. Modular adder designs using optimal reversible and fault tolerant gates in field-coupled QCA nanocomputing. Int. J. Theor. Phys., 2018, 57(5), 1356-1375.
[http://dx.doi.org/10.1007/s10773-018-3664-z]
[http://dx.doi.org/10.1007/s10773-018-3664-z]
[60]
Al-Shafi, A.; Aneek, R.H.; Bahar, A.N. Universal reversible gate in quantum-dot cellular automata (QCA): A multilayer design paradigm. Int. J. Grid Distrib. Comput., 2017, 10(1), 43-50.
[http://dx.doi.org/10.14257/ijgdc.2017.10.1.05]
[http://dx.doi.org/10.14257/ijgdc.2017.10.1.05]
[61]
Chabi, A.M.; Roohi, A.; Khademolhosseini, H.; Sheikhfaal, S.; Angizi, S.; Navi, K.; DeMara, R.F. Towards ultra-efficient QCA reversible circuits. Microprocess. Microsyst., 2017, 49, 127-138.
[http://dx.doi.org/10.1016/j.micpro.2016.09.015]
[http://dx.doi.org/10.1016/j.micpro.2016.09.015]
[62]
Bhat, S.M.; Ahmed, S. Design of ultra-efficient reversible gate based 1-bit full adder in QCA with power dissipation analysis. Int. J. Theor. Phys., 2019, 58(12), 4042-4063.
[http://dx.doi.org/10.1007/s10773-019-04271-9]
[http://dx.doi.org/10.1007/s10773-019-04271-9]
[63]
Akbarian, F.; Mosleh, M. Towards nanoscale fault-tolerant logical circuits using proposed robust majority voter in quantum-dot cellular automata technology. Nano Commun. Netw., 2023, 38, 100468.
[http://dx.doi.org/10.1016/j.nancom.2023.100468]
[http://dx.doi.org/10.1016/j.nancom.2023.100468]
[64]
Kandasamy, N.; Ahmad, F.; Ajitha, D.; Raj, B.; Telagam, N. Quantum dot cellular automata-based scan flip-flop and boundary scan regis-ter. J. Inst. Electron. Telecommun. Eng., 2023, 69(1), 535-548.
[http://dx.doi.org/10.1080/03772063.2020.1831411]
[http://dx.doi.org/10.1080/03772063.2020.1831411]
[65]
Heikalabad, S.R.; Asfestani, M.N.; Hosseinzadeh, M. A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis. J. Supercomput., 2018, 74(5), 1994-2005.
[http://dx.doi.org/10.1007/s11227-017-2206-4]
[http://dx.doi.org/10.1007/s11227-017-2206-4]
[66]
Srivastava, S.; Asthana, A.; Bhanja, S.; Sarkar, S. QCAPro - An error-power estimation tool for QCA circuit design. In: 2011 IEEE Interna-tional Symposium of Circuits and Systems (ISCAS), 15-18 May 2011Rio de Janeiro, Brazil2011.
[http://dx.doi.org/10.1109/ISCAS.2011.5938081]
[http://dx.doi.org/10.1109/ISCAS.2011.5938081]
[67]
Walus, K.; Dysart, T.J.; Jullien, G.A.; Budiman, R.A. QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata. IEEE Trans. Nanotechnol., 2004, 3(1), 26-31.
[http://dx.doi.org/10.1109/TNANO.2003.820815]
[http://dx.doi.org/10.1109/TNANO.2003.820815]
[68]
Amiri, M.; Dousti, M.; Mohammadi, M. Design and implementation of carry-save adder using quantum-dot cellular automata. J. Supercomput., 2023, 1-4.
[http://dx.doi.org/10.1007/s11227-023-05532-5]
[http://dx.doi.org/10.1007/s11227-023-05532-5]
[69]
Das, J.C.; Debnath, B.; De, D. Quantum‐dot cellular automata based design for overflow detection in two’s complement arithmetic operation. Int. J. Numer. Model., 2023, 36(5), e3091.
[http://dx.doi.org/10.1002/jnm.3091]
[http://dx.doi.org/10.1002/jnm.3091]
[70]
Sen, B.; Saran, D.; Saha, M.; Sikdar, B.K. Synthesis of reversible universal logic around QCA with online testability. 2011.International Symposium on Electronic System Design, 19-21 December 2011Kochi, India2011
[http://dx.doi.org/10.1109/ISED.2011.53]
[http://dx.doi.org/10.1109/ISED.2011.53]
[71]
Thapliyal, H.; Ranganathan, N. Conservative QCA gate (CQCA) for designing concurrently testable molecular QCA circuits. 2009 22nd International Conference on VLSI Design, 2009, pp. 511-516.
[72]
Chabi, A.M.; Roohi, A.; DeMara, R.F.; Angizi, S.; Navi, K.; Khademolhosseini, H. Cost-efficient QCA reversible combinational circuits based on a new reversible gate. 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS), 2015.
[http://dx.doi.org/10.1109/CADS.2015.7377779]
[http://dx.doi.org/10.1109/CADS.2015.7377779]
[73]
Ahmadpour, S.S.; Heidari, A.; Navimpour, N.J.; Asadi, M.A.; Yalcin, S. An efficient design of multiplier for using in nano-scale IoT sys-tems using atomic silicon. IEEE Internet Things J., 2023, 10(16), 14908-14909.
[http://dx.doi.org/10.1109/JIOT.2023.3267165]
[http://dx.doi.org/10.1109/JIOT.2023.3267165]
[74]
Sen, B.; Dutta, M.; Goswami, M.; Sikdar, B.K. Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability. Microelectronics, 2014, 45(11), 1522-1532.
[http://dx.doi.org/10.1016/j.mejo.2014.08.012]
[http://dx.doi.org/10.1016/j.mejo.2014.08.012]
[75]
Sen, B.; Dutta, M.; Sikdar, B.K. Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing. Microelectronics, 2014, 45(2), 239-248.
[http://dx.doi.org/10.1016/j.mejo.2013.11.008]
[http://dx.doi.org/10.1016/j.mejo.2013.11.008]
[76]
Sasamal, T.N.; Singh, A.K.; Mohan, A. Design of cost-efficient qca reversible circuits via clock zone-based crossover. Int. J. Theor. Phys., 2018, 57(10), 3127-3140.
[http://dx.doi.org/10.1007/s10773-018-3830-3]
[http://dx.doi.org/10.1007/s10773-018-3830-3]
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