Login Register Cart 0
Generic placeholder image

Micro and Nanosystems

Editor-in-Chief

ISSN (Print): 1876-4029
ISSN (Online): 1876-4037

Back
Journal Home About Journal Editorial Board Journal Insight Current Issue Volumes/Issues
Subscribe
Research Article

Performance Analysis of SOI-Tunnel FET with AlxGa1-xAs Channel Material

Author(s): Sweta Chander and Sanjeet Kumar Sinha*

Volume 15, Issue 3, 2023

Published on: 27 October, 2023

Page: [185 - 188] Pages: 4

DOI: 10.2174/1876402914666220511143102

Price: $65

Abstract

Background: Tunnel Field-effect transistor (TFETs) has appeared as a promising candidate due to its steep slope (SS<60 mV/dec), which can be used for low-power applications.

Objectives: Authors investigated AlxGa1-xAs as the channel material in Silicon-on-Insulator (SOI) TFETs and compared it to other existing channel materials, SiGe, Ge, Si, Ge, Strained Si, and GaAs.

Methods: For the entire device study, the mole fraction x = 0.2 has been used in AlxGa1-xAs channel material. The direct energy bandgap for Al0.2Ga0.8As has been used because the mole fraction is less than 0.4. The Al0.2Ga0.8As-based device has been analyzed in terms of Direct Current (DC) and Alternating Current (AC) characteristics using the Synopsys TCAD tool.

Results: The proposed device offers enhanced switching speed with a high on/off ratio of ~1012 and a steep subthreshold swing of 30 mv/dec As a channel material, Al0.2Ga0.8As also enhances the miller capacitance of the device, which is one of the essential requirements of the device performance.

Conclusion: In next-generation devices, Al0.2Ga0.8As as channel material and TFET device based on this channel material act as a promising contender for low-power applications.

Keywords: Tunnel Field Effect Transistor, Silicon-on-Insulator, Subthreshold Swing, Miller capacitance, Threshold voltage, Ion/Ioff current

« Previous Next »
[1]
Zhang, W.Z.; Seabaugh, A. Low-subthreshold-swing tunnel transistors. IEEE Elec. Dev. Lett., 2006, 27(4), 297-300.
[http://dx.doi.org/10.1109/LED.2006.871855]
[2]
Sinha, S.K.; Chander, S. Investigation of DC performance of Ge-Source pocket silicon-on-insulator tunnel field effect transistor in Nano regime. Inderscience. Int. J. Nanoparticles, 2021, 13(1), 13-20.
[http://dx.doi.org/10.1504/IJNP.2021.114896]
[3]
Mookerjea, S.; Krishnan, R.; Datta, S.; Narayanan, V. Effective capacitance and drive current for tunnel FET (TFET) CV/I estimation. IEEE Trans. Elect. Dev., 2009, 56(9), 2092-2098.
[4]
Koswatta, S.O.; Nikonov, D.E.; Lundstrom, M.S. “Computational Study of Carbon Nanotube Pin Tunnel FETs” I; IEDM Tech. Dig, 2005, pp. 518-521.
[5]
Sinha, S.K.; Chaudhury, S. Simulation and analysis of quantum capacitance in single-gate MOSFET, double-gate MOSFET and CNTFET devices for nanometre regime. IEEE International Conference on Communication, Devices and Intelligent Systems; 2012 28-29 Dec; Kolkata, India;, 2012, 157-160.
[http://dx.doi.org/10.1109/CODIS.2012.6422160]
[6]
Sinha, S.K.; Chaudhury, S. Oxide thickness effect on Quantum Capacitance in single gate MOSFET and CNTFET devices. In 2012 Annual IEEE India Conference, 2012, pp. 042-046.
[http://dx.doi.org/ 10.1109/INDCON.2012.6420586.]
[7]
Ahish, S.; Sharma, D.; Kumar, Y.B.N.; Vasantha, M.H. Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using Gaussian doping. IEEE Trans. on Elect. Dev., 2015, 63(1), 288-295.
[8]
Seabaugh, A.C.; Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. the IEEE , 2010, pp. 2095-2110. 98(12), 2095-2110.
[http://dx.doi.org/ 10.1109/JPROC.2010.2070470]
[9]
Verhulst, A.S.; Leonelli, D.; Rooyackers, R.; Groeseneken, G. Drain voltage dependent analytical model of tunnel field-effect transistors. J. Appl. Phys., 2011, 110(2), 024510.
[http://dx.doi.org/10.1063/1.3609064]
[10]
Solomon, P.M.; Lauer, I.; Majumdar, A.; Teherani, J.T.; Luisier, M.; Cai, J.; Koester, S.J. Effect of uniaxial strain on the drain current of a heterojunction tunneling field-effect transistor. IEEE Elec. Dev. Lett., 2011, 32(4), 464-466.
[http://dx.doi.org/10.1109/LED.2011.2108993]
[11]
Boucart, K.; Ionescu, A.M. Double-Gate Tunnel FET with High-$\kappa $ gate dielectric. IEEE Trans. Elect. Dev., 2007, 54(7), 1725-1733.
[12]
Sinha, S.K.; Chaudhury, S. Impact of temperature variation on CNTFET device characteristics. 2013 IEEE International Conference on Control, Automation, Robotics & Embedded Systems, In 2013 Dec 16-18Jabalpur, India2013, 1-5.
[http://dx.doi.org/ 10.1109/CARE.2013.6733774]
[13]
Lu, B.; Lu, H.; Zhang, Y.; Zhang, Y.; Cui, X.; Lv, Z.; Liu, C. A charge-based capacitance model for double-gate tunnel FETs with closed-form solution. IEEE Trans. Elect. Dev., 2017, 65(1), 299-307.
[14]
Lyu, Z.; Lu, H.; Zhang, Y.; Zhang, Y.; Lu, B.; Cui, X.; Zhao, Y. A fully analytical current model for tunnel field-effect transistors consid-ering the effects of source depletion and channel charges. IEEE Trans. Elect. Dev., 2018, 65(11), 4988-4994.
[15]
Conzatti, F.; Pala, M.G.; Esseni, D.; Bano, E.; Selmi, L. Strain-induced performance improvements in InAs nanowire tunnel FETs. IEEE Trans. Elect. Dev., 2012, 59(8), 2085-2092.
[16]
Ford, A.C.; Yeung, C.W.; Chuang, S.; Kim, H.S.; Plis, E.; Krishna, S.; Javey, A. Ultrathin body InAs tunneling field-effect transistors on Si substrates. Appl. Phys. Lett., 2011, 98(11), 113105.
[http://dx.doi.org/10.1063/1.3567021]
[17]
Sinha, S.K.; Kumar, K.; Chaudhury, S. CNTFET: The emerging Post- CMOS device. In 2013 IEEE International Conference on Signal Processing and Communication, 2013 Dec 12-14Noida, India2013, pp. 372-374.
[18]
Kao, K. -.H.; Verhulst, A.S.; Vandenberghe, W.G.; Sorée, B.; Groeseneken, G.; DeMeyer, K. Modeling the impact of junction angles in tunnel field-effect transistors. Sol. Sta. Elect, 2012, 69, 31-37.
[19]
Singh, P.K.; Baral, K.; Chander, S.; Kumar, S.; Tripathy, M.R.; Singh, A.K.; Jit, S. Impact of gate dielectrics on analog/rf performance of double gate tunnel field effect transistor. In 2019 3rd IEEE International Conference on Electronics, Materials Engineering & Nano Technology, 2019 Aug 29-31; Kolkata, India; 2019, pp. 1-5.
[http://dx.doi.org/10.1109/IEMENTech48150.2019.8981283]
[20]
Chauhan, R.; Abhinav, A.; Kumar, A.; Rai, S. A comparative study of junctionless dual material double gate Silicon on Insulator (SOI) and Silicon on Nothing (SON) MOSFET. In 2017 4th International Conference on Power, Control and Embedded Systems (ICPCES), 9-11 Mar; Allahabad, India; 2017,; , 2017, pp. 1-7.
[http://dx.doi.org/10.1109/ICPCES.2017.8117648]

Rights & Permissions Print Cite
Article Metrics
1
© 2024 Bentham Science Publishers | Privacy Policy