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Recent Advances in Computer Science and Communications

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ISSN (Print): 2666-2558
ISSN (Online): 2666-2566

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General Research Article

A Hybrid Branch Prediction Approach For High-Performance Processors

Author(s): Sweety Nain* and Prachi Chaudhary

Volume 15, Issue 6, 2022

Published on: 10 February, 2021

Article ID: e040921191297 Pages: 7

DOI: 10.2174/2666255814666210210163616

Price: $65

Abstract

Background: In a parallel processor, the pipeline cannot fetch the conditional instructions with the next clock cycle, leading to a pipeline stall. Therefore, conditional instructions create a problem in the pipeline because the proper path can only be known after the branch execution. To accurately predict branches, a significant predictor is proposed for the prediction of the conditional branch instruction.

Methods: In this paper, a single branch prediction and a correlation branch prediction scheme are applied to the different trace files by using the concept of saturating counters. Further, a hybrid branch prediction scheme is proposed, which uses both global and local branch information, providing more accuracy than the single and correlation branch prediction schemes.

Results: Firstly, a single branch prediction and correlation branch prediction technique are applied to the trace files using saturating counters. By comparison, it can be observed that a correlation branch prediction technique provides better results by enhancing the accuracy rate of 2.25% than the simple branch prediction. Further, a hybrid branch prediction scheme is proposed, which uses both global and local branch information, providing more accuracy than the single and correlation branch prediction schemes. The results suggest that the proposed hybrid branch prediction schemes provide an increased accuracy rate of 3.68% and 1.43% than single branch prediction and correlation branch prediction.

Conclusion: The proposed hybrid branch prediction scheme gives a lower misprediction rate and higher accuracy rate than the simple branch prediction scheme and correlation branch prediction scheme.

Keywords: Pipeline, branch prediction, static branch prediction, dynamic branch prediction, accuracy rate.

[1]
S. Nain, and P. Chaudhary, "Implemented static branch prediction schemes for the parallelism processors", In In 2019 IEEE International Conference on Machine Learning, Big Data, Cloud and Parallel Computing, 2019, pp. 79-83
[2]
G. Steven, R. Anguera, C. Egan, F. Steven, and L. Vintan, "Dynamic branch prediction using neural networks", In In Proceedings IEEE Euromicro Symposium on Digital Systems Design, 2001, pp. 178-185
[http://dx.doi.org/10.1109/DSD.2001.952279]
[3]
P.P. Ravale, and S.S. Apte, "Design of a branch prediction unit of a microprocessor based on superscalar architecture using VLSI In", In 2010 2nd International Conference on Computer Engineering and Technology
Vol. 3, pp. 355-360, 2010 [http://dx.doi.org/10.1109/ICCET.2010.5485221]
[4]
S. Nain, and P. Chaudhary, "Branch prediction techniques used in pipeline processors: A review", Int. J. Pure Appl. Math., vol. 119, no. 15, pp. 2843-2851, 2018.
[5]
B. Calder, D. Grunwald, M. Jones, J. Martin, M. Mozer, and B. Zorn, "Evidence-based static branch prediction using machine learning", ACM Trans. Program. Lang. Syst., vol. 19, no. 1, pp. 188-222, 2004.
[http://dx.doi.org/10.1145/239912.239923]
[6]
C. C. Cheng, The schemes and performances of dynamic branch predictors Tech. Rep. 2000, pp. 1-18
[7]
S. Mittal, "A survey of techniques for dynamic branch prediction", Concurr. Comput., vol. 31, no. 1, p. 4666, 2019.
[8]
S. Nain, and P. Chaudhary, "Design and FPGA based implementation of 1-bit dynamic branch predictor for the parallelism processor", J. Crit. Rev., vol. 7, no. 9, pp. 1156-1162, 2020.
[9]
D.A. Jimenez, and C. Lin, "Neural methods for dynamic branch prediction", ACM Trans. Comput. Syst., vol. 20, no. 4, pp. 369-397, 2002.
[http://dx.doi.org/10.1145/571637.571639]
[10]
S. Manne, A. Klauser, and D. Grunwald, "Branch prediction using selective branch inversion", In 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999, pp. 48-56
[11]
D. Tarjan, and K. Skadron, "Merging path and gshare indexing in perceptron branch prediction", ACM Trans. Archit. Code Optim., vol. 2, no. 3, pp. 280-300, 2005.
[http://dx.doi.org/10.1145/1089008.1089011]
[12]
V. R. Kulkarni, and N. Ketan, A review of branch prediction schemes and a study of branch predictors in modern microprocessors. 2016, pp. 1-10
[13]
A. Seznec, J. San Miguel, and J. Albericio, "Practical Multidimensional Branch Prediction", IEEE Micro, vol. 36, no. 3, pp. 10-19, 2016.
[http://dx.doi.org/10.1109/MM.2016.33]
[14]
P.Z. Shah, and S.U. Prabhu, "Hybrid learning-based branch predictor", Int. J. Eng. Res. Technol., vol. 3, no. 8, pp. 1135-1139, 2014.
[15]
J. Albericio, J.S. Miguel, N.E. Jerger, and A. Moshovos, "Wormhole: Wisely predicting multidimensional branches", In 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2015, pp. 509-520

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