Search Result "drain-induced-barrier-lowering"
Analytical Modeling of Threshold Voltage and Drain-Induced-Barrier- Lowering Variations Due to Gate Length Fluctuation in Nanometer MOSFETs
Journal: Recent Advances in Electrical & Electronic Engineering
Volume: 10 Issue: 2 Year: 2017 Page: 128-133
Author(s): Lu Weifeng,Wang Guangyi,Lin Mi,Sun Lingling
Transition from Conventional FETs to Novel FETs, SOI, Double Gate, Triple Gate, and GAA FETS
Ebook: Nanoscale Field Effect Transistors: Emerging Applications
Volume: 1 Year: 2023
Author(s):
Doi: 10.2174/9789815165647123010005
An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET
Journal: Nanoscience & Nanotechnology-Asia
Volume: 9 Issue: 4 Year: 2019 Page: 504-511
Author(s): Sikha Mishra,Urmila Bhanja,Guru Prasad Mishra
CMOS Compatible Single-Gate Single Electron Transistor (SG-SET) Based Hybrid SETMOS Logic
Ebook: Nanoscale Field Effect Transistors: Emerging Applications
Volume: 1 Year: 2023
Author(s):
Doi: 10.2174/9789815165647123010010
An Extensive Simulation Study of Gate Underlap Influence on Device Performance of Surrounding Gate In0.53Ga0.47As/InP Hetero Field Effect Transistor
Journal: Nanoscience & Nanotechnology-Asia
Volume: 10 Issue: 2 Year: 2020 Page: 157-165
Author(s): Soumya S. Mohanty,Urmila Bhanja,Guru P. Mishra
Device Structure Modifications in Conventional Tunnel Field Effect Transistor (TFET) for Low-power Applications
Ebook: Nanoelectronics Devices: Design, Materials, and Applications (Part I)
Volume: 1 Year: 2023
Author(s):
Doi: 10.2174/9789815136623123010008
FinFET Advancements and Challenges: A State-of-the-Art Review
Ebook: Nanoelectronics Devices: Design, Materials, and Applications (Part I)
Volume: 1 Year: 2023
Author(s):
Doi: 10.2174/9789815136623123010011
Ge-Channel Nanosheet FinFETs for Nanoscale Mixed Signal Application
Ebook: Nanoelectronic Devices and Applications
Volume: 1 Year: 2024
Author(s): Dinesh Kumar Dash
Doi: 10.2174/9789815238242124010015
II-VI Semiconductor-based Thin-Film Transistor Sensor for Room Temperature Hydrogen Detection From Idea to Product Development
Ebook: Nanoelectronics Devices: Design, Materials, and Applications (Part I)
Volume: 1 Year: 2023
Author(s):
Doi: 10.2174/9789815136623123010010
An Analytical Drain Current Model for Dual-material Gate Graded - channel and Dual-oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET
Journal: Nanoscience & Nanotechnology-Asia
Volume: 9 Issue: 2 Year: 2019 Page: 291-297
Author(s): Hind Jaafar,Abdellah Aouaj,Ahmed Bouziane,Benjamin Iñiguez