Abstract
The shrinking of the device parameters' dimensions could be a solution for
improving the performance and high transistor density of traditional MOSFETs.
However, the short-channel effects could create a problem in the performance of the
device. This chapter examines and performs comprehensive simulations of the standard
junctionless double-gate transistor. In this research, silicon thickness and work function
engineering are used to better understand the junctionless transistor's operation. As
silicon thickness increases, the junctionless double-gate FET's performance begins to
decline. Additionally, the typical double-gate junctionless FET is modelled, and the
change in silicon thickness, work function, gate dielectric, and doping concentration is
studied. The findings of the analysis and simulation are found to be quite similar. As a
result, the device is referred to as a rectangular core-shell double-gate junctionless
transistor because of the core being sandwiched between the two shells of the device
(RCS-DGJLT). While the core-shell is doped with acceptor impurities in an n-type
RCS-DGJLT, donor impurities are used in the shells. The device performance
parameters have been improved such that IOFF of order ~10-14A, ION ~10-5A, ION/IOFF ~109
,
SS nearly 68.9mV/decade, DIBL nearly 52.6mV/V are obtained at a total silicon
thickness of 12nm and channel length of 20nm. The effect of channel length variation
on RCS-DGJLT is also studied. RCS-DGJLT is found to have better performance than
conventional DGJLT.