Login Register Cart 0
Generic placeholder image

Current Nanoscience

Editor-in-Chief

ISSN (Print): 1573-4137
ISSN (Online): 1875-6786

Back
Journal Home About Journal Editorial Board Journal Insight Current Issue Volumes/Issues
Subscribe
Mini-Review Article

Review of the Nanoscale FinFET Device for the Applications in Nano-regime

Author(s): Shams Ul Haq and Vijay Kumar Sharma*

Volume 19, Issue 5, 2023

Published on: 26 December, 2022

Page: [651 - 662] Pages: 12

DOI: 10.2174/1573413719666221206122301

Price: $65

Abstract

Background: The insatiable need for low-power and high-performance integrated circuit (IC) results in the development of alternative options for metal oxide semiconductor field effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of transistors whose size must be scaled while increasing performance. As the size of the transistor shrinks for the new technology node, the control of the gate over the channel also reduces, leading to sub-threshold leakage. The non-planar technology is the potential methodology to design the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the most valuable non-planar technology. High sub-threshold slope, better short channel effect (SCE) control, high current drive strength, low dopant-prompted variations, and decreased power dissipation are the prominent features of FinFET technology.

Objective: FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore, in this review paper, the different geometrical structures, working operations, design challenges, future aspects, and the different configurations of FinFETs are presented. The performance of the different configurations of a 1-bit full adder is evaluated and compared.

Methods: An overview of FinFET evolution from the planar MOSFET, along with its architecture supported by the requisite equations, is presented in the paper. Besides this, it also gives an insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT) variations, width quantization, design challenges, and the future of FinFETs. A comparative study of FinFET-based 1-bit full adder using various techniques is done to compute and compare the leakage power, delay, and power delay product (PDP).

Results: The full adders using FinFETs show less leakage power and PDP. The AND-OR logicbased hybrid full adder using FinFETs shows the least energy consumption per switching. Fin- FET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to the full adder using MOSFET technology. The low power FinFET-based full adder shows a 54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results signify the effect of multi-gates in curbing the leakage power dissipation.

Conclusion: MOSFET faces the practical challenge of device scaling and SCEs at lower technology nodes. It initiates the multi-gate technology for future system generation. FinFET has the capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The geometrical structure of FinFET plays a key role to improve the performance metrics in an ultrananoscale regime.

« Previous Next »
Graphical Abstract

[1]
Sharma, V.K.; Pattanaik, M. Design of low leakage variability aware ONOFIC CMOS standard cell library. J. Circuits Syst. Comput., 2016, 25(11), 1650134.
[http://dx.doi.org/10.1142/S0218126616501346]
[2]
Amiri, I.S.; Mohammadi, H.; Hosseinghadiry, M. Device Physics, Modeling, technology, and analysis for silicon MESFET; Springer International Publishing: Cham, Switzerland, 2019.
[http://dx.doi.org/10.1007/978-3-030-04513-5]
[3]
Zhu, W.J.; Ma, T.P. Temperature dependence of channel mobility in HfO/sub 2/-gated NMOSFETs. IEEE Electron Device Lett., 2004, 25(2), 89-91.
[http://dx.doi.org/10.1109/LED.2003.822648]
[4]
Ashraf, N.S.; Alam, S.; Alam, M. Review of Research on Scaled Device Architectures and Importance of Lower Substrate Temperature Operation of-MOSFETs.New Prospects of Integrating Low Substrate Temperatures with Scaling-Sustained Device Architectural Innovation; Springer, 2016, pp. 1-6.
[http://dx.doi.org/10.1007/978-3-031-02027-8_1]
[5]
Nayak, K.; Agarwal, S.; Bajaj, M.; Murali, K.V.R.M.; Rao, V.R. Random dopant fluctuation induced variability in undoped channel Si gate all around nanowire n-MOSFET. IEEE Trans. Electron Dev., 2015, 62(2), 685-688.
[http://dx.doi.org/10.1109/TED.2014.2383352]
[6]
Devi, K.G.; Tejasree, K.; Sri, M.K.; Pravallika, M. Energy reduction of D-Flipflop using 130 nm CMOS technology. J. VLSI Circuit. Syst., 2021, 3(2), 34-41.
[7]
Mahmoud, H.A.H. A low power architectural framework for automated surveillance system with low bit rate transmission. Int. J. Commun. Netw. Inf. Secur., 2021, 13(1), 115-124.
[8]
Al-Zu’bi, H.; Al-Khaleel, O.; Shatnawi, A. FPGA implementation of data flow graphs for digital signal processing applications. Int. J. Commun. Netw. Inf. Secur., 2021, 13(1), 92-114.
[9]
Bhosale, A.; Patil, S.; Dhepe, V.; Banosde, K.; Kakde, R.; Teltumade, R.; Lengare, D. 3-D numerical study of effect of urea injector location and intake cone geometry on SCR performance. Inter. J. Innov. Res. Sci. Stud., 2022, 5(2), 47-58.
[http://dx.doi.org/10.53894/ijirss.v5i2.378]
[10]
Suba, G.M.; Kumerasen, M. SettingsA hybrid RFOA-DDAO based voltage transfer gain enhancement through ultra lift luo converter and cockcroft-walton multiplier. Int. J. Intell. Syst. Appl. Eng., 2022, 10(1), 17-27.
[http://dx.doi.org/10.18201/ijisae.2022.263]
[11]
Babu, P.A.; Pasupuleti, V.N.; Modugula, S.M.; Kadava, D.; Maguluri, R.; Mopidevi, N.S. Millimeter-wave power amplifier ics for high dynamic range signals. Inter. J. Commun. Comput. Technol., 2021, 10(2), 15-36.
[12]
Rao, K.M.; Kishore, M.N.D.; Yogesh, M.P.; Saheb, S.K.A.; Hemanth, K. Triple frequency micro strip patch antenna using ground slot technique. Nat. J. Antennas Propag., 2021, 3(2), 1-5.
[13]
Rostami, M.; Mohanram, K. Dual-Vth independent-gate FinFETs for low power logic circuits. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., 2011, 30(3), 337-349.
[http://dx.doi.org/10.1109/TCAD.2010.2097310]
[14]
Lee, J.H.; Bosman, G.; Green, K.R.; Ladwig, D. Gate leakage current noise in ultra-thin gate oxide MOSFET’s. Noise in Physical Systems and 1/F Fluctuations; ICNF, 2001, pp. 165-168.
[http://dx.doi.org/10.1142/9789812811165_0037]
[15]
Bhoj, AN; Jha, NK Design of logic gates and flip-flops in highperformance FinFET technology. IEEE transactions on very large scale integration (VLSI) systems, 2013, 21(11), 1975-1988.
[http://dx.doi.org/10.1109/TVLSI.2012.2227850]
[16]
Riaz, A.; Sharma, V.K. A novel low power 4:2 compressor using FinFET devices. Analog Integr. Circuits Signal Process., 2022, 112(1), 127-139.
[http://dx.doi.org/10.1007/s10470-022-01989-1]
[17]
Kajal; Sharma, V.K. A novel low power technique for FinFET domino OR Logic. J. Circuits Syst. Comput., 2021, 30(7), 2150117.
[http://dx.doi.org/10.1142/S0218126621501176]
[18]
Reddy, M.N; Panda, D.K A comprehensive review on finfet in terms of its device structure and performance matrices; Silicon, 2022. 1-6.
[http://dx.doi.org/10.1007/s12633-022-01929-8]
[19]
Maszara, WP; Lin, MR. FinFETs—Technology and circuit design challenges. In 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013 Sep 16 (pp. 3-8). IEEE.
[20]
Jalili, B.; Aghaee, N.; Jalili, P.; Domiri Ganji, D. Novel usage of the curved rectangular fin on the heat transfer of a double-pipe heat exchanger with a nanofluid. Case Stud. Therm. Eng., 2022, 35, 102086.
[http://dx.doi.org/10.1016/j.csite.2022.102086]
[21]
Jalili, B; Sadighi, S; Jalili, P Ganji, DD Numerical analysis of MHD nanofluid flow and heat transfer in a circular porous medium containing a Cassini oval under the influence of the Lorentz and buoyancy forces. Heat Transfer, 2022, 51(7), 6122-6138.
[http://dx.doi.org/10.1002/htj.22582]
[22]
Jalili, B.; Jalili, P.; Sadighi, S.; Ganji, D.D. Effect of magnetic and boundary parameters on flow characteristics analysis of micropolar ferrofluid through the shrinking sheet with effective thermal conductivity. Zhongguo Wuli Xuekan, 2021, 71, 136-150.
[http://dx.doi.org/10.1016/j.cjph.2020.02.034]
[23]
Jalili, B.; Sadighi, S.; Jalili, P.; Ganji, D.D. Characteristics of ferrofluid flow over a stretching sheet with suction and injection. Case Stud. Therm. Eng., 2019, 14, 100470.
[http://dx.doi.org/10.1016/j.csite.2019.100470]
[24]
Jalili, P.; Ganji, D.; Jalili, B.; Ganji, D. Evaluation of electro-osmotic flow in a nanochannel via semi-analytical method. Therm. Sci., 2012, 16(5), 1297-1302.
[http://dx.doi.org/10.2298/TSCI1205297J]
[25]
Yahyazadeh, H.; Ganji, D.; Yahyazadeh, A.; Khalili, T.; Jalili, P.; Jouya, M. Evaluation of natural convection flow of a nanofluid over a linearly stretching sheet in the presence of magnetic field by the differential transformation method. Therm. Sci., 2012, 16(5), 1281-1287.
[http://dx.doi.org/10.2298/TSCI1205281Y]
[26]
Jalili, B.; Ghafoori, H.; Jalili, P. Investigation of carbon nano-tube (CNT) particles effect on the performance of a refrigeration cycle. Int. J. Mater. Sci. Innov., 2014, 2, 8-17.
[27]
Sharma, V.K.; Pattanaik, M. VLSI scaling methods and low power CMOS buffer circuit. J. Semicond., 2013, 34(9), 095001.
[http://dx.doi.org/10.1088/1674-4926/34/9/095001]
[28]
Sharma, V.K.; Pattanaik, M. Process, voltage and temperature variations aware low leakage approach for nanoscale CMOS circuits. J. Low Power Electron., 2014, 10(1), 45-52.
[http://dx.doi.org/10.1166/jolpe.2014.1293]
[29]
Sharma, V.K. CNTFET circuit-based wide fan-in domino logic for low power applications. J. Circuits Syst. Comput., 2022, 31(2), 2250036.
[http://dx.doi.org/10.1142/S0218126622500360]
[30]
Mushtaq, U.; Sharma, V.K. Performance analysis for reliable nanoscaled FinFET logic circuits. Analog Integr. Circuits Signal Process., 2021, 107(3), 671-682.
[http://dx.doi.org/10.1007/s10470-020-01765-z]
[31]
Koh, M.; Mizubayashi, W.; Iwamoto, K.; Murakami, H.; Ono, T.; Tsuno, M.; Mihara, T.; Shibahara, K.; Miyazaki, S.; Hirose, M. Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current. IEEE Trans. Electron Dev., 2001, 48(2), 259-264.
[http://dx.doi.org/10.1109/16.902724]
[32]
Thompson, S.E.; Armstrong, M.; Auth, C.; Alavi, M.; Buehler, M.; Chau, R.; Cea, S.; Ghani, T.; Glass, G.; Hoffman, T.; Jan, C.H.; Kenyon, C.; Klaus, J.; Kuhn, K.; Ma, Z.; Mcintyre, B.; Mistry, K.; Murthy, A.; Obradovic, B.; Nagisetty, R.; Nguyen, P.; Sivakumar, S.; Shaheed, R.; Shifren, L.; Tufts, B.; Tyagi, S.; Bohr, M.; El-Mansy, Y. A 90 nm logic technology featuring strained-silicon. IEEE Trans. Electron Dev., 2004, 51(11), 1790-1797.
[http://dx.doi.org/10.1109/TED.2004.836648]
[33]
Wang, B.; Huang, W.; Chi, L.; Al-Hashimi, M.; Marks, T.J.; Facchetti, A. High-k gate dielectrics for emerging flexible and stretchable electronics. Chem. Rev., 2018, 118(11), 5690-5754.
[http://dx.doi.org/10.1021/acs.chemrev.8b00045] [PMID: 29785854]
[34]
Mistry, K.; Allen, C.; Auth, C.; Beattie, B.; Bergstrom, D.; Bost, M.; Brazier, M.; Buehler, M.; Cappellani, A.; Chau, R.; Choi, C.H.A. A 45 nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. In. IEEE International Electron Devices Meeting 2007 Dec 10, pp. 247-250). IEEE, 2007.
[35]
Mushtaq, U.; Sharma, V.K. Design and analysis of INDEP FinFET SRAM cell at 7 nm technology. Int. J. Numer. Model., 2020, 33(5), e2730.
[http://dx.doi.org/10.1002/jnm.2730]
[36]
Xu, N. Effectiveness of strain solutions for next-generation MOSFETs; University of California: Berkeley, 2012.
[37]
Kajal, Sharma VK. FinFET: A Beginning of Non-planar Transistor Era; Springer: Singapore, 2020, pp. 139-159.
[38]
Lee, H.J.; Callender, S.; Rami, S.; Shin, W.; Yu, Q.; Marulanda, J.M. Intel 22 nm low-power FinFET (22FFL) process technology for 5G and beyond. 2020 IEEE Custom Integrated Circuits Conference (CICC), 2020, pp. 1-7.
[http://dx.doi.org/10.1109/CICC48029.2020.9075914]
[39]
Kajal; Sharma, V.K. Design and Simulation of FinFET Circuits at Different Technologies. In: 6th International Conference on Inventive Computation Technologies (ICICT); , 2021; pp. 1-6.
[40]
Jovanovic, V.; Suligoj, T.; Nanver, L. Crystallographic silicon-etching for ultra-high aspect-ratio FinFET. ECS Trans., 2008, 13(1), 313-320.
[http://dx.doi.org/10.1149/1.2911512]
[41]
Hoffman, T.Y. Integrating high-k/metal gates: Gate-first or gate-last? Solid State Technol., 2010, 53(3), 20-21.
[42]
Lee, Y.J.; Luo, G.L.; Hou, F.J.; Chen, M.C.; Yang, C.C.; Shen, C.H.; Wu, W.F.; Shieh, J.M.; Yeh, W.K. Ge GAA FETs and TMD finfets for the applications beyond Si-A review. IEEE J. Electron Devices Soc., 2016, 4(5), 286-293.
[http://dx.doi.org/10.1109/JEDS.2016.2590580]
[43]
Sharma, V.K.; Pattanaik, M. A reliable ground bounce noise reduction technique for nanoscale CMOS circuits. Int. J. Electron., 2015, 102(11), 1852-1866.
[http://dx.doi.org/10.1080/00207217.2014.996786]
[44]
Moshgelani, F; Al-Khalili, D; Rozon, C Ultra-low leakage arithmetic circuits using symmetric and asymmetric FinFETs. J. Electr. Comput. Eng., 2013, 2013
[http://dx.doi.org/10.1155/2013/454392]
[45]
Cerdeira, A.; Estrada, M.; Alvarado, J.; Garduño, I.; Contreras, E.; Tinoco, J.; Iniguez, B.; Kilchytska, V.; Flandre, D. Review on double-gate MOSFETs and FinFETs modeling. Facta universitatis-series. Electr. Energ., 2013, 26(3), 197-213.
[46]
Subramanian, V.; Parvais, B.; Borremans, J.; Mercha, A.; Linten, D.; Wambacq, P.; Loo, J.; Dehan, M.; Gustin, C.; Collaert, N.; Kubicek, S.; Lander, R.; Hooker, J.; Cubaynes, F.; Donnay, S.; Jurczak, M.; Groeseneken, G.; Sansen, W.; Decoutere, S. Planar bulk MOSFETs versus FinFETs: An analog/RF perspective. IEEE Trans. Electron Dev., 2006, 53(12), 3071-3079.
[http://dx.doi.org/10.1109/TED.2006.885649]
[47]
Riaz, A.; Sharma, V.K. Performance comparison for FinFET nanoscale static and domino logic circuits. Int. J. Nanosci., 2022, 21(2), 2250012-2250154.
[http://dx.doi.org/10.1142/S0219581X22500120]
[48]
Hossain, M.Z.; Hossain, M.A.; Islam, M.S.; Rahman, M.M.; Chowdhury, M.H. Electrical characteristics of trigate finfet. Global J. Res. Eng. Electri. Electron. Eng., 2011, vol. 11 issue 7.
[49]
Narendar, V.; Rai, S.; Mishra, R.A. Design of high-performance digital logic circuits based on FinFET technology. Int. J. Comput. Appl., 2012, 41(20), 40-44.
[http://dx.doi.org/10.5120/5812-8104]
[50]
Huq, SI; Nafreen, M; Rahman, T; Bhadra, S. Comparative study of full adder circuit with 32nm MOSFET, DG-FinFET and CNTFET. In: 2017 4th International Conference on Advances in Electrical Engineering (ICAEE); 2017 Sep 28 (pp. 38-43). IEEE.
[51]
Sharma, V.K. A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime. Austr. J. Electr. Electron. Eng., 2021, 18(4), 217-236.
[http://dx.doi.org/10.1080/1448837X.2021.1966957]
[52]
Kajal; Sharma, V.K. Reliability and PVT simulation of FinFET circuits using Cadence Virtuoso. In: 5th International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (ICEECCOT); , 2021; pp. 344-349.
[53]
Wang, Z.; Chen, L.; Yin, M. Analysis and characterization of layout dependent effect for advance FinFET circuit design. Microelectronics, 2022, 125, 105449.
[http://dx.doi.org/10.1016/j.mejo.2022.105449]
[54]
Nabavi, M.; Ramezankhani, F.; Shams, M. Optimum pMOS-to-nMOS width ratio for efficient sub-threshold CMOS circuits. IEEE Trans. Electron Dev., 2016, 63(3), 916-924.
[http://dx.doi.org/10.1109/TED.2016.2517446]
[55]
Dolatshah, A.; Abbasian, E.; Nayeri, M.; Sofimowloodi, S. A sub-threshold 10T FinFET SRAM cell design for low-power applications. AEU Int. J. Electron. Commun., 2022, 157, 154417.
[http://dx.doi.org/10.1016/j.aeue.2022.154417]
[56]
Yang, Y.; Jha, N.K. FinPrin: FinFET logic circuit analysis and optimization under PVT variations. IEEE Transactions on Very Large Scale Integration (VLSI). Systems., 2013, 22(12), 2462-2475.
[57]
Haq, S.U.; Sharma, V.K. Challenges in Low Power VLSI Design. A Review 2021.
[http://dx.doi.org/10.1109/ICECA52323.2021.9676055]
[58]
Kajal; Sharma, V.K. Design and simulation for NBTI aware logic gates. Wirel. Pers. Commun., 2021, 120(2), 1525-1542.
[http://dx.doi.org/10.1007/s11277-021-08522-z]
[59]
Abbasian, E.; Gholipour, M.; Birla, S. A single-bitline 9T SRAM for low-power near-threshold operation in FinFET technology. Arab. J. Sci. Eng., 2022, 47, 14543-14559.
[http://dx.doi.org/10.1007/s13369-022-06821-6]
[60]
Mohapatra, S.K.; Pradhan, K.P.; Singh, D.; Sahu, P.K. The role of geometry parameters and fin aspect ratio of sub-20 nm SOI-FinFET: an analysis towards analog and RF circuit design. IEEE Trans. Nanotechnol., 2015, 14(3), 546-554.
[http://dx.doi.org/10.1109/TNANO.2015.2415555]
[61]
Poljak, M.; Jovanović, V.; Suligoj, T. Properties of bulk FinFET with high-κ gate dielectric and metal gate electrode. Proc. MIPRO, 2008, 73-78.
[62]
Banerjee, S.; Sarkar, E.; Mukherjee, A. Effect of Fin Width and Fin Height on Threshold Voltage for Tripple Gate Rectangular FinFET. Techno International Journal of Health, Engineering. Manage. Sci., 2018.
[63]
Champac, V.; Garcia Gervacio, J. Designing with FinFETs and Process Variation Impact.Timing Performance of Nanometer Digital Circuits Under Process Variations; Springer: Cham, 2018, pp. 143-163.
[http://dx.doi.org/10.1007/978-3-319-75465-9_7]
[64]
Damrongplasit, N.; Kim, S.H.; Shin, C.; Liu, T.J.K. Impact of gate line-edge roughness (LER) versus random dopant fluctuations (RDF) on germanium-source tunnel FET performance. IEEE Trans. Nanotechnol., 2013, 12(6), 1061-1067.
[http://dx.doi.org/10.1109/TNANO.2013.2278153]
[65]
Kajal; Sharma, V.K. Design of low power AOI FinFET circuits at 7nm. In: 4th International Conference on Electronics, Communication and Aerospace Technology (ICECA); , 2020; pp. 136-142.
[66]
Lahbib, I.; Doukkali, M.A.; Martin, P.; Imbert, G. Hot carrier injection and negative bias temperature instability induced NMOS and PMOS degradation on CMOS Ring Oscillator. In: Annual Reliability and Maintainability Symposium (RAMS); , 2016; pp. 1-7.
[http://dx.doi.org/10.1109/RAMS.2016.7448024]
[67]
Zimpeck, A; Meinhardt, C; Artola, L; Reis, R Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs; Springer International Publishing, 2021.
[http://dx.doi.org/10.1007/978-3-030-68368-9]
[68]
Boukortt, N.; Lenka, T.; Patanè, S.; Crupi, G. Effects of varying the fin width, fin height, gate dielectric material, and gate length on the DC and RF performance of a 14-nm SOI FinFET structure. Electronics (Basel), 2021, 11(1), 91.
[http://dx.doi.org/10.3390/electronics11010091]
[69]
Jovanović, V.; Suligoj, T.; Poljak, M.; Civale, Y.; Nanver, L.K. Ultra-high aspect-ratio FinFET technology. Solid-State Electron., 2010, 54(9), 870-876.
[http://dx.doi.org/10.1016/j.sse.2010.04.021]
[70]
Choi, J.H.; Murthy, J.; Roy, K. The effect of process variation on device temperature in FinFET circuits. In: 2007 IEEE/ACM International Conference on Computer-Aided Design; pp. 747-751. IEEE, 2007.
[71]
Lederer, D.; Parvais, B.; Mercha, A.; Collaert, N.; Jurczak, M.; Raskin, J.P.; Decoutere, S. Dependence of FinFET RF performance on fin width. In: Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 18-20 January 2006; San Diego, CA, USA, IEEE, 2006.
[72]
Mushtaq, U.; Sharma, V.K. Design of 6T FinFET SRAM cell at 7nm. In: International Conference on Communication and Electronics Systems (ICCES); , 2019; pp. 104-108.
[http://dx.doi.org/10.1109/ICCES45898.2019.9002138]
[73]
Li, R.; Liu, Y.; Zhang, K.; Zhao, C.; Zhu, H.; Yin, H. Punch through stop layer optimization in bulk FinFETs. In: 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 28-31 October 2014; Guilin, China, IEEE, 2014.
[http://dx.doi.org/10.1109/ICSICT.2014.7021523]
[74]
Marella, S.K.; Trivedi, A.R.; Mukhopadhyay, S.; Sapatnekar, S.S. Optimization of FinFET-based circuits using a dual gate pitch technique. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD); , 2015; pp. 758-763.
[http://dx.doi.org/10.1109/ICCAD.2015.7372646]
[75]
Cui, T.; Xie, Q.; Wang, Y.; Nazarian, S.; Pedram, M. 7nm FinFET standard cell layout characterization and power density prediction in near-and super-threshold voltage regimes. In: International Green Computing Conference; , 2014; pp. 1-7.
[http://dx.doi.org/10.1109/IGCC.2014.7039170]
[76]
Huo, Q.; Wu, Z.; Huang, W.; Wang, X.; Tang, G.; Yao, J.; Liu, Y.; Zhao, X.; Zhang, F.; Li, L.; Liu, M. A novel general compact model approach for 7 nm technology node circuit optimization from device perspective and beyond. IEEE J. Electron Devices Soc., 2020, 8, 295-301.
[http://dx.doi.org/10.1109/JEDS.2020.2980441]
[77]
Sharma, V.K. Design and simulation of reliable low power CMOS logic gates. J. Inst. Electron. Telecommun. Eng., 2020, 1-11.
[http://dx.doi.org/10.1080/03772063.2020.1847700]
[78]
Chesbrough, H. The future of open innovation: The future of open innovation is more extensive, more collaborative, and more engaged with a wider variety of participants. Res. Technol. Manag., 2017, 60(1), 35-38.
[http://dx.doi.org/10.1080/08956308.2017.1255054]
[79]
Madhavi, K.B.; Tripathi, S.L. Strategic review on different materials for FinFET structure performance optimization. In: IOP Conference Series: Materials Science and Engineering. Vol. 988; No. 1. IOP Publishing,. , 2020.
[80]
Ding, Y.; Luo, X.; Shang, E.; Hu, S.; Chen, S.; Zhao, Y. A device design for 5 nm Logic FinFET technology. In: China Semiconductor Technology International Conference (CSTIC); , 2020; pp. 1-5.
[http://dx.doi.org/10.1109/CSTIC49141.2020.9282491]
[81]
Mohapatra, E.; Dash, T.P.; Jena, J.; Das, S.; Maiti, C.K. Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes. SN Appl. Sci., 2021, 3(5), 540.
[http://dx.doi.org/10.1007/s42452-021-04539-y]
[82]
Hassan Agha, F.N.A.; Naif, Y.H.; Shakib, M.N. Review of nanosheet transistors technology. Tikrit J. Eng. Sci., 2021, 28(1), 40-48.
[http://dx.doi.org/10.25130/tjes.28.1.05]
[83]
Schuegraf, K.; Abraham, M.C.; Brand, A.; Naik, M.; Thakur, R. Semiconductor logic technology innovation to achieve sub-10 nm manufacturing. IEEE J. Electron Devices Soc., 2013, 1(3), 66-75.
[http://dx.doi.org/10.1109/JEDS.2013.2271582]
[84]
Hussain, S.; Hasan, M.; Agrawal, G.; Hasan, M. A high‐performance full swing 1‐bit hybrid full adder cell. IET Circuits Dev. Syst., 2022, 16(3), 210-217.
[http://dx.doi.org/10.1049/cds2.12097]
[85]
Rahin, A.B.; Rahin, V.B. FinFET-based Full Adder using SDTSPC logic with high performance. Int. J. Mechatron. Electr. Comput. Technol., 2020, 10(38), 4773-4778.
[86]
Prasad, M.V.; Kumar, K.N. Low Power FinFET Based Full Adder Design. Int. J. Adv. Res. Comput. Commun. Eng., 2007, 6(8), 328-335.
[87]
Tahrim, A.; Chin, H.C.; Lim, C.S.; Tan, M.L. Design and performance analysis of 1-bit FinFET full adder cells for sub-threshold region at 16 nm process technology. J. Nanomater., 2015, 2015, Article ID: 726175.
[88]
Vejendla, N. Performance analysis of adder circuits using FINFET’S. J. Circ. Syst., 2017, 5(3), 1.
[89]
Saraswat, R.; Akashe, S.; Babu, S. Designing and simulation of full adder cell using FINFET technique. In: 7th International Conference on Intelligent Systems and Control (ISCO), 04-05 January 2013; Coimbatore, India, IEEE, 2013.
[http://dx.doi.org/10.1109/ISCO.2013.6481159]
[90]
Sharma, S; Soni, G Comparative study of finfet based 1-bit full adder cell implemented using TG And CMOS Logic Styles At 10, 22 And 32nm. IOSR J. VLSI Signal Process. (IOSR-JVSP), 6, 26-35.
[91]
Vendhan, M.A. Analysis on circuit metrics of 1-bit finfet adders realized using distinct logic structures. Indian J. Sci. Technol., 2019, 12(26), 1-4.
[http://dx.doi.org/10.17485/ijst/2019/v12i26/145499]
[92]
Huq, S.I. Performance Analysis of 6-Transistor Full Adder Circuit using PTM 32 nm Technology LP-MOSFETs and DG-FinFETs. J. Eng. Appl. Sci. (Asian Res. Publ. Netw.), 2020, 15(2), 501-507.
[93]
Gehlot, H.; Lodhi, M.E. Analysis of proposed FinFET based full adder using CMOS logic style. Inter. Res. J. Eng. Technol., 2019, 6 [IRJET].
[94]
Kahlon, J.; Kumar, P.; Garg, A.; Gupta, A. Low power and temperature compatible FinFET based full adder circuit with optimised area. In: International Conference on Advances in Computing, Communications and Informatics (ICACCI); , 2016; pp. 2121-2125.
[http://dx.doi.org/10.1109/ICACCI.2016.7732365]
[95]
Hajare, R.; Lakshminarayana, C. Design and software characterization of finFET based full adders. Inter. J. Reconfigur. Embed. Syst. (IJRES), 2019, 8(1), 51.
[http://dx.doi.org/10.11591/ijres.v8.i1.pp51-60]
[96]
Florance, D.R.; Prabhakar, B. Design of FinFET and GnrFET based full adder cell using multiplexer selection logic. 20-22 January 2022, Tirunelveli, India, IEEE 2022.
[http://dx.doi.org/10.1109/ICSSIT53264.2022.9716389]

Rights & Permissions Print Cite
© 2024 Bentham Science Publishers | Privacy Policy