Abstract
Introduction: The 3D integrated circuit technology, which smooths out the massive increase in transistors on a chip by stacking numerous silicon layers vertically, is quickly becoming a revolutionary technology. Thermal issues are more relevant for 3D Network-on-Chip (NoC) systems than their 2D counterparts.
Methods: This paper presents a novel Vertically-Partially-Connected 3D-Network on-chip architecture that reduces the total length of interconnects and reduces the number of 3D routers. We also present an efficient XYZ routing technique for thermal management. The proposed algorithm distributes traffic based on the number of layers and congestion to achieve chip heat balancing, avoid high peak temperatures, improve average packet latency, and extend chip service life.
Results: Simulation results showed that the routing technique reduces the peak temperature of the chip by an average of 17 °C compared to the exiting routing algorithms, with minimized negative impact on performance.
Conclusion: Furthermore, the Vertically-Partially-Connected 3D-Network on-chip implemented in this study using VHDL exhibits improved area occupation by reducing the number of employed LUT in the FPGA compared to previous works.
Keywords: 3D network-on-chip, partially-connected 3D-NoC, XYZ routing, heat balance, FPGA, noxim.
Graphical Abstract
[1]
Y. Xie, J. Cong and S. Sapatnekar, Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures”, Design and Micro-architectures., vol. 20. Springer: New York, 2010, pp. 194-196.
[http://dx.doi.org/10.1007/978-1-4419-0784-4]
[http://dx.doi.org/10.1007/978-1-4419-0784-4]
[2]
K. Messaoudi, S. Toumi, and E-B. Bourennane, "network-on-chip especially for video coding applications using multilayer mesh topology", Recent Adv. Electr. Electron. Eng., vol. 12, no. 3, pp. 247-256, 2019.
[http://dx.doi.org/10.2174/2352096511666180525124330]
[http://dx.doi.org/10.2174/2352096511666180525124330]
[3]
V. Tiwari, K. Khare, and S. Shandilya, "An efficient 4X4 mesh structure with a combination of two NoC router architecture", Int. J. Sensors Wirel. Commun. Control, vol. 11, no. 2, pp. 169-180, 2021.
[http://dx.doi.org/10.2174/2210327910666200306132045]
[http://dx.doi.org/10.2174/2210327910666200306132045]
[4]
W. Lafi, D. Lattard, and A. Jerraya, An efficient hierarchical router for 3D NoC architecture. 21st IEEE International Symposium on Rap-id System Prototyping (RSP 2010), 8 Jun 2018 Fairfax, Virginia, USA, 2018.
[5]
Cheng Liu, Lei Zhang, and Yinhe Han, "Vertical interconnects squeezing in symmetric 3D mesh network-on-chip", National
Basic Research Program of China. (973) under grant No.
2011CB302503.
[6]
A. Sheibanyrad, F. Pétrot, A. Jantsch, Eds., 3D Integration for NoC-based SoC Architectures., Springer, 2011.
[7]
A. Benhaoues, E. Bourennane, C. Tanougast, H. Mayache, S. Toumi, and K. Messaoudi, Implementation of Universal Digital Architecture using 3D-NoC for Mobile Terminal. 2014 International Conference on Control, Decision and Information Technologies (CoDIT), 03-05 November 2014, Metz, France, 2011, pp. 595-600.
[http://dx.doi.org/10.1109/CoDIT.2014.6996962]
[http://dx.doi.org/10.1109/CoDIT.2014.6996962]
[8]
J.L. Hennessy, D.A. Patterson, Eds., Design and management of 3D chip multiprocessors using network-in-memory. Proceedings of International Symposium on Computer Architecture, 17-21 Jun, 2006, Boston, MA, USA, 2006, pp. 130-141.
[9]
J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, and C. Das, A novel dimensionally-decomposed router for on-chip communication in 3D architectures. Proceedings of International Symposium on Computer Architecture, 09 Jun, 2007, California, San Diego, USA, 2007, pp. 138-149.
[http://dx.doi.org/10.1145/1250662.1250680]
[http://dx.doi.org/10.1145/1250662.1250680]
[10]
K.H. Seyed, S. Reza, H. Maysam, and R. Mohsen, A new modified version of Advanced Encryption Standard based algorithm for image encryption. International Conference on Electronics and Information Engineering, 09 Jun, 2007, California, San Diego, USA, 2010.
[11]
P. Sudeep, Exploring serial vertical interconnects for 3dics. Proceedings of the 46th Annual Design Automation Conference, 26-31 Jul, 2009, San Francisco, CA, USA, 2009, p. 581.
[12]
M. Bahmani, A. Sheibanyrad, F. Petrot, and F. Dubois, "A deadlock-free distributed routing algorithm for vertically partially connected 3d-nocs", IEEE Trans. Comput., vol. 62, no. 3, pp. 609-615, 2011.
[13]
A.B. Kahng, B. Li, L-S. Peh, and K. Samadi, "B.Li, L.S.Peh, K.Samadi, “ORION2.0: a power-area simulator for inter connection net-works”, IEEE Trans. Very Large Scale Integr. (VLSI)", Syst., vol. 20, no. 1, pp. 191-196, 2012.
[http://dx.doi.org/10.1109/TVLSI.2010.2091686]
[http://dx.doi.org/10.1109/TVLSI.2010.2091686]
[14]
B. Black, Die stacking (3D) microarchitecture. Proceeding of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, 09-13 Dec, 2006, Orlando, FL, USA, 2006, pp. 469-479.
[15]
W.C. Tsai, S.J. Chen, Y.H. Hu, and M.L. Chiang, "Network cognitive traffic control: A fluidity-aware on-chip communication", electronics, vol. 9, no. 10, p. 1667, 2020.
[http://dx.doi.org/10.3390/electronics9101667]
[http://dx.doi.org/10.3390/electronics9101667]
[16]
K. Mahsa, M. Mehdi, H. Seyed, and R. Seyedahaei, "Thermal management in 3d networks-on-chip using dynamic linksharing", Microprocess. Microsyst., vol. 52, no. July, pp. 69-79, 2017.
[http://dx.doi.org/10.1016/j.micpro.2017.05.011]
[http://dx.doi.org/10.1016/j.micpro.2017.05.011]
[17]
M. Said, A. Shalaby, and F. Gebali, "Thermal-aware network-on-chips: Single- and cross-layered approaches", Future Gener. Comput. Syst., vol. 91, pp. 61-85, 2019.
[http://dx.doi.org/10.1016/j.future.2018.08.041]
[http://dx.doi.org/10.1016/j.future.2018.08.041]
[18]
K.C. Chen, C.H. Chao, and A.Y. Wu, "Thermalaware 3D Network-on-Chip (3D NoC) designs: Routing algorithms and thermal managements", IEEE Circuits Syst. Mag., vol. 15, no. 4, pp. 45-69, .
[http://dx.doi.org/10.1109/MCAS.2015.2484139]
[http://dx.doi.org/10.1109/MCAS.2015.2484139]
[19]
F. Dubois, A. Sheibanyrad, F. Petrot, and M. Bahmani, "Elevator-first: A deadlock-free distributed routing algorithm for vertically partially connected 3d-nocs", IEEE Trans. Comput., vol. 62, no. 3, pp. 609-615, 2013.
[20]
M. Zhu, J. Lee, and K. Choi, "First limit on WIMP cross section with low background crystal detector", In Physics Letters B, vol. 633, pp. 201-208, 2016.
[21]
M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and H. Tenhunen, "Agent-based on-chip network using efficient selection method", In: 19th International Conference on VLSI and System-on-Chip, 3 Oct, 2011, pp. 284-289.
[22]
J. Lee, and K. Choi, "A deadlock-free routing algorithm requiring no virtual channel on 3d-nocs with partial vertical connections", Networks on Chip (NoCS), pp. 1-2, 2013.
[http://dx.doi.org/10.1109/NoCS.2013.655840]
[http://dx.doi.org/10.1109/NoCS.2013.655840]
[23]
R. Salamat, M. Ebrahimi, and N. Bagherzadeh, "An adaptive, low restrictive and fault resilient routing algorithm for 3d network-onchip", In: 23rd Euromicro. Int. Conf. Parall., Distrib. Net.Based
Process, 4 Mar, 2015, Turku, Finland, 2015, pp. 392-395.
[24]
S. Ronak, K. Misagh, E. Masoumeh, and B. Nader, "LEAD: An adaptive 3d-noc routing algorithm with queuing-theory based analytical verification", IEEE Trans. Comput., vol. 67, no. 8, 2018.
[http://dx.doi.org/10.1109/TC.2018.2801298]
[http://dx.doi.org/10.1109/TC.2018.2801298]
[25]
H. Ying, A. Jaiswal, and K. Hofmann, Deadlock-free routing algorithm for 3- dimension Networks-on-Chip with reduced vertical channel density topologies., High Perform. Comput. Simulat. Conf. HPCS, 2012.
[http://dx.doi.org/10.1109/HPCSim.2012.6266923]
[http://dx.doi.org/10.1109/HPCSim.2012.6266923]
[26]
P. Mukherjee, N. Chatterjee, and S. Chattopadhyay, "Thermalaware detour routing in 3D NoCs", J. Parallel Distrib. Comput., vol. 144, pp. 230-245, 2020.
[http://dx.doi.org/10.1016/j.jpdc.2020.04.010]
[http://dx.doi.org/10.1016/j.jpdc.2020.04.010]
[27]
Z. Shirmohammadi, M. Mahmoudi, and M. Rostamnezhad, "Int-TAR: An Intelligent Thermal-Aware Routing Algorithm for 3D NoC", J. Electrical Comput. Engi. Innov., vol. 10, no. 1, pp. 47-56, 2022.
[http://dx.doi.org/10.22061/JECEI.2021.7750.428]
[http://dx.doi.org/10.22061/JECEI.2021.7750.428]
[28]
S.C. Lee, and T.H. Han, "Q-Function-Based Traffic- and Thermal-Aware Adaptive Routing for 3D Network-on-Chip", Electronics, vol. 9, no. 3, p. 392, 2020.
[http://dx.doi.org/10.3390/electronics9030392]
[http://dx.doi.org/10.3390/electronics9030392]
[29]
C. Chih-Hao, J. Kai-Yuan, W. Hao-Yu, W. Jia-Cheng, and W. An-Yeu, Traffic-and thermal-aware run-time thermal management scheme for 3D NoC systems. 2010 Fourth ACM/IEEE Int. Symp. Networks-on-Chip, 3 May, 2010, Grenoble, France, 2010, pp. 223-230.
[30]
C.H. Chao, K.Y. Jheng, H.Y. Wang, J.C. Wu, and A.Y.C. Wu, Transport layer assisted routing for non-stationary irregular mesh of ther-mal-aware 3D network-on-chip systems. Proceedings of the IEEE International SOC Conference (SOCC), 2011, pp. 284-289.
[31]
J. Wang, H. Gu, K. Wang, Y. Yang, and K. Wang, "DRTL: A heat-balanced deadlock-free routing algorithm for 3D topology network-on-chip", Microprocess. Microsyst., vol. 45, pp. 95-104, 2016.
[http://dx.doi.org/10.1016/j.micpro.2016.04.002]
[http://dx.doi.org/10.1016/j.micpro.2016.04.002]
[32]
C.X. Thomas, L. Pasi, and T. Hannu, "A new modified version of advanced encryption standard based algorithm for image encryption", In: International Conference on Electronics and Information Engineering, 01-03 Aug, 2010, Kyoto, Japan, 2010, pp. 1-141.
[http://dx.doi.org/10.1109/ICEIE.2010.5559865]
[http://dx.doi.org/10.1109/ICEIE.2010.5559865]
[33]
C. Wang, W.H. Hu, S.E. Lee, and N. Bagherzadeh, "Area and power-efficient innovative congestion-aware Network-on-Chip architecture", J. Systems Archit., vol. 57, no. 1, pp. 24-38, 2011.
[http://dx.doi.org/10.1016/j.sysarc.2010.10.009]
[http://dx.doi.org/10.1016/j.sysarc.2010.10.009]
[34]
K. Gaffour, M.K. Benhaoua, A.H. Benyamina, and H.E. Zahaf, "A new congestion-aware routing algorithm in network-on-chip: 2D and 3D comparison", Int. J. Comput. Appl., pp. 1-9, 2019.
[http://dx.doi.org/10.1080/1206212X.2019.1679529]
[http://dx.doi.org/10.1080/1206212X.2019.1679529]
[37]
F.A. Samman, "Microarchitecture and implementation of Networks-on-Chip with a flexible concept for communication media sharing", 2010.
[38]
M. Bahmani, A. Sheibanyrad, F. Pétrot, F. Dubois, and P. Durante, "A 3D-NoC router implementation exploiting vertically-partiallyconnected topologies", In: 2012 IEEE Computer Society Annual
Symposium on VLS, 19 Aug, 2012,, Amherst, MA, USA, 2012, pp. 9-14.
[http://dx.doi.org/10.1109/ISVLSI.2012.19]
[http://dx.doi.org/10.1109/ISVLSI.2012.19]
[39]
"FabrizioFazzino, Maurizio Palesi and David Patti. Noxim: Networkon- chip simulator", http://sourceforge. net/projects/noxim
[40]
Wei Huang, G Shougata, V Siva, S Karthik, S Kevin, and R T Mircea, "Hotspot: A compact thermal modeling methodology for early-stage vlsi design", IEEE Trans. on Very Large Scale Integr. (VLSI) Sys., , vol. 14, no. 5, pp. 501-513, 2006.
[41]
J.K. Yuan, C.C. Hao, W.H. Yu, and W.A. Yeu, "Traffic-thermal mutual-coupling co-simulation platform for threedimensional network-on-chip", In: VLSI Design Automation and Test (VLSI-DAT),
2010 Int. Sym. on, 2010, pp. 135-138.
[42]
H. Vinay, and V. Sarma, "Energy-efficient operation of multicore processors by dvfs, task migration and active cooling", IEEE Trans. Comput., vol. 63, no. 2, pp. 349-360, 2014.
[43]
M. Mojtahedi, A.M. Fard, R. Moghaddam, and S. Newton, "Sustainable vehicle routing problem for coordinated solid waste management", J. Ind. Inf. Integr., vol. 23, p. 100220, 2021.
[http://dx.doi.org/10.1016/j.jii.2021.100220]
[http://dx.doi.org/10.1016/j.jii.2021.100220]
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