Generic placeholder image

Micro and Nanosystems

Editor-in-Chief

ISSN (Print): 1876-4029
ISSN (Online): 1876-4037

Research Article

The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

Author(s): Heranmoy Maity *, Arindam Biswas, Arup K. Bhattacharjee and Anita Pal

Volume 12, Issue 3, 2020

Page: [146 - 148] Pages: 3

DOI: 10.2174/2213476X06666190916141330

Abstract

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block.

Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block.

Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Keywords: Reversible logic gate, decoder, quantum cost, garbage output, constant input, 2:4 decoder.

Graphical Abstract

[1]
Haghparast, M.; Bolhassani, A. Optimized parity preserving quantum reversible full adder/subtractor. J. Circuits Syst. Comput., 2016, 14, 12.
[http://dx.doi.org/10.1142/S0219749916500192]
[2]
Maity, H.; Barik, A.K.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. Design of quantum cost, garbage output and delay optimized BCD to excess-3 and 2’s complement code converter. J. Circuits Syst. Comput., 2018, 27, 11.
[http://dx.doi.org/10.1142/S0218126618501840]
[3]
Bennett, C.H. Logical reversibility of computation. IBM J. Res. Develop., 1973, 17, 525-532.
[http://dx.doi.org/10.1147/rd.176.0525]
[4]
Maity, H.; Biswas, A.; Bhattacharjee, A.K. Design of quantum cost efficient MOD-8 synchronous UP/DOWN counter using reversible logic gate. Proceedings of the International Conference on Computational Science and Engineering (ICCSE 2016), Kolkata, India2016, pp. 3-6.
[http://dx.doi.org/10.1201/9781315375021-2]
[5]
Feynman, R. Quantum mechanical computers. Optics News, 1985, 11(2), 11-20.
[6]
Peres, A. Reversible logic and quantum computers. Phys. Rev. A Gen. Phys., 1985, 32(6), 3266-3276.
[http://dx.doi.org/10.1103/PhysRevA.32.3266] [PMID: 9896493]
[7]
Maity, H.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate. Int. J. Quant. Inf., 2018, 16, 8.
[http://dx.doi.org/10.1142/S0219749918500168]
[8]
Maity, H.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. Design of quantum cost efficient 4-Bit reversible universal shift register. Conference on Device for Integrated Circuits (DevIC 2017), Kalyani, India2017, pp. 44-47.
[9]
Misra, N.K.; Sen, B.; Wairya, S.; Bhoi, B. Testable novel parity-preserving reversible gate and low-cost quantum decoder design in 1D Molecular-QCA. J. Circuits Syst. Comput., 2017, 26(9), 26.
[http://dx.doi.org/10.1142/S0218126617501456]
[10]
Maity, H.; Biswas, A.; Bhattacharjee, A.K.; Pal, A. Design of reversible combinational circuits using new reversible logic gate. J. Eng. Sci. Tech. Rev., 2018, 11, 170-172.
[http://dx.doi.org/10.25103/jestr.115.21]
[11]
Maity, H.; Biswas, A.; Pal, A.; Bhattacharjee, A.K. Design of BCD to excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate. Int. J. Quant. Inf., 2018, 16(07)1850061
[http://dx.doi.org/10.1142/S0219749918500612]
[12]
Rahman, M.R. Cost efficient fault tolerant decoder in reversible logic synthesis. Int. J. Comput. Appl., 2014, 108, 7-12.
[13]
Jamal, L.; Alam, M.M.; Babu, H.M.H. An efficient approach to design a reversible control unit of a processor. Sustain. Comput. Inf. Syst., 2013, 3, 286-294.
[http://dx.doi.org/10.1016/j.suscom.2013.06.001]
[14]
Shamsujjoha, M.; Hasan Babu, H.M.; Jamal, L. Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis. Microelectronics J., 2013, 44, 519-537.
[http://dx.doi.org/10.1016/j.mejo.2013.02.005]
[15]
Shamsujjoha, M.; Hasan Babu, H.M. A low power fault tolerant reversible decoder using MOS transistors. Conference on Embedded Systems, 2013, pp. 368-373.
[http://dx.doi.org/10.1109/VLSID.2013.216]
[16]
Noor Mahammad, S.; Veezhinathan, K. Constructing online testable circuits using reversible logic. IEEE Trans. Instrum. Meas., 2010, 59, 101-109.
[http://dx.doi.org/10.1109/TIM.2009.2022103]
[17]
Perkowski, M.; Lukac, M.; Kerntopf, P.; Pivtoraiko, M.; Folgheraiter, M.; Choi, Y.W.; Kim, J-W.; Lee, D.; Hwangbo, W.; Kim, H. A hierarchical approach to computer-aided design of quantum circuits. Paper 228, Electrical and Computer Engineering Faculty, Portland State University. Publications and Presentations; Portland State University: Portland, WA, United States, 2003.
[18]
Misra, N.K.; Wairya, S.; Singh, V.K. Evolution of structure of some binary group based n-bit comparator, n-to-2n decoder by reversible technique. Int. J. VLSI Des. Commun. Syst., 2015, 5, 9-30.
[http://dx.doi.org/10.5121/vlsic.2014.5502]
[19]
Maity, H.; Banerjee, S.; Biswas, A.; Pal, A.; Bhattacharjee, A.K. Design of reversible shift register using reduced number of logic gate. Micro Nanosyst., 2019, 12(1), 33-37.
[http://dx.doi.org/10.2174/1876402911666190617112734]

© 2024 Bentham Science Publishers | Privacy Policy