The last couple of years have been very busy for the semiconductor industry and researchers. The rapid speed of production channel length reduction has brought lithographic challenges to semiconductor modeling. These include stress optimization, transistor reliability and efficient circuit design with respect to interconnects, power and leakage at the chip level. This e-book focuses on the latest semiconductor techniques devised to address these issues. It should be a useful resource for electronic engineers and semiconductor chip designers.

This book surveys the major and newly developed techniques for semiconductor strain metrology. Semiconductor strain metrology has emerged in recent years as a topic of great interest to researchers involved in thin film and nanoscale device characterization. This e-book employs a tutorial approach to explain the principles and applications of each technique specifically tailored for graduate students and postdoctoral researchers. Selected topics include optical, electron beam, ion beam and synchrotron x-ray techniques. Unlike earlier references, this e-book specifically discusses strain metrology as applied to semiconductor devices with both depth and focus.

I joined NEC in 1968 and was assigned to the circuit development department of the computer division. My first work was the circuit design of the switching mode power supply (SMPS) for the mainframe of the computer system. My job area was expanded to development of the design rule and to standardization of all over the electric and electronics parts for the non-logic circuit. Non-logic circuit was categorized to except the gate-array which forms the logic circuit of the mainframe. The experiment of SMPS was considered to be dangerousness and no one wanted to design. Therefore, my development of the power supply system (PSS) including the circuit design of SMPS was continued. The electric current of the mainframe and the supercomputer was reached to several thousand amperes. The critical problem of PSS was the heat dissipation and the electromagnetic interference (EMI) against the logic circuit. In 1992, the full-scale R&D of EMC became necessary hastily. I was nominated and transferred to the chief managing researcher of the established EMC engineering center in NEC Laboratories. I had believed that the switching mode circuit (SMC) including the digital circuit and SMPS circuit will be improved greatly if the EMC problem is solved. However the deep R&D was difficult because the actual fruits in every year were required strongly. Therefore, his knowledge of the science concerning EMC was not deepened enough. However I could understand the actual status of technologies of the electronics and electrics widely and the basic knowledge about how to approach the science as well as R&D could be learned. During this time, I completed PhD course and received the PhD. degree from Kyushu University, lectured in Kyushu University and Tohoku University for one year each, and executed several national projects by the cooperation of his colleague in NEC and of the supporters in the industrial society and academia. These are considered to be my best harvest in NEC Laboratories. I had decided to continue R&D for solving EMC problem of SMC after his retirement and to try the commercialization of the fruit of R&D. I established ICAST which is the abbreviation of the innovative circuit and system technologies in 2005. The solitary electromagnetic (SEMW) theory was advocated and the novel technologies including the low impedance lossy line (LILL) and the matched impedance lossy line (MILL) were invented based on the SEMW theory.

Two purposes exist in this eBook. The first is to be validated the SEMW theory by the academia and the industrial society. The second is the contribution to the growth of the industry in the world by the technologies of LILL and MILL.

It is well known that Intersymbol (ISI) Interference is a limiting factor in many communication environments where it causes an irreducible degradation of the bit error rate (BER) thus imposing an upper limit on the data symbol rate. In order to overcome the ISI problem, an equalizer is implemented in those systems. Among the three types of equalizers - non-blind, semi-blind and blind – the blind equalizer has the benefit of bandwidth saving and there is no need of going through a training phase. Blind equalization algorithms are essentially adaptive filtering algorithms designed such that they do not require the external supply of a desired response to generate the error signal in the output of the adaptive equalization filter. The algorithms generate an estimate of the desired response by applying a nonlinear transformation to sequences involved in the adaptation process. This nonlinearity is designed to minimize a cost function that is implicitly based on higher order statistics (HOS) according to one approach, or calculated directly according to the Bayes rules. The Whole Story behind Blind Adaptive Equalizers/ Blind Deconvolution gives the readers a full understanding on blind deconvolution. The e-book covers a variety of blind deconvolution/equalization methods based on both cost functions and Bayes rules where simulation results are supplied to support the theory. These include the Maximum Entropy density approximation technique and the Edgeworth Expansion approach used in various blind equalizers. It also describes the relationship between the cost function approach and the approach taken according to Bayes rules. The e-book deals also with the effect of various system parameters (such as the step-size parameter or the equalizer's tap length) have on the obtained equalization performance. This e-book will be of particular interest to advanced communications engineering undergraduate students, graduate students, university instructors and signal processing researchers.

The number of transistors in integrated circuits doubles every two years, as stipulated by Moore’s law, and this has been the driving force for the huge development of the microelectronics industry in the past 50 years – currently advanced to the nanometric scale. This e-book is dedicated to electronic noises and parasites, accounting for issues involving substrate coupling and interconnections, in the perspective of the 3D integration: a second track for enhancing integration, also compatible with Moore’s law. This reference explains the modeling of 3D circuits without delving into the latest advances, but highlights crucial problems, for instance electro-thermo-mechanical problems, which could be addressed through 3D modeling. The book also explains electromagnetic interferences , at different modeling levels (device and circuit) oriented towards 3D integration technologies. It also covers substrate noise, such as disturbances of digital blocks, power bounces, phase noise in oscillators, both at the device level, such as carriers or field fluctuations, and circuit levels. The entanglement between interconnect and substrate is also discussed. This e-book serves as a reference for advanced graduates or researchers in the field of micro and nano electronics interested in topics relevant to electromagnetic interference or the ‘noise’ domain, at device or circuit and system levels

This ebook is a collection of cutting edge articles from the 2009 Workshop on Microcavities and their Applications (WOMA 2009). It gives readers an overview of state-of-the-art opto electronic research on nano and micro cavities presented by leading experts in the field. Two major themes covered in this ebook are (i) wave- and ray-chaos in open microcavity systems and (ii) opto-electronic applications in nano and micro cavities. The book concludes with a description of recent advances in 2D whispering-gallery-mode microresonators. This ebook should be a very useful reference for any serious opto-electronics researcher.