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Nanoscience & Nanotechnology-Asia

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ISSN (Print): 2210-6812
ISSN (Online): 2210-6820

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Research Article

Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits

Author(s): Rumi Rastogi*, Sujata Pandey and Mridula Gupta

Volume 10, Issue 5, 2020

Page: [696 - 708] Pages: 13

DOI: 10.2174/2210681209666190513120054

Price: $65

Abstract

Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits.

Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits.

Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit.

Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively.

Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

Keywords: MTCMOS, parallel transistor, variable-width, charge-recycling, modified-charge recycling, leakage power, footer.

Graphical Abstract

[1]
Yemisscioglu, G.; Lee, P. Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor. IET Comput. Digit. Tech., 2015, 9(5), 239-247.
[2]
Rastogi, R.; Pandey, S. Implementing low power dynamic adders in MTCMOS technology. Poceedings of the IEEE international Conference on Electronics and Communication Systems, ICECS-2015, Coimbatore, India, 26-27 February, 2015.
[3]
Rastogi, R.; Pandey, S. Leakage power reduction in MTCMOS based high speed adders. Proceedings of the IEEE International Conference on Computer, Communication and Control, IC-4-2015, Indore, India, 10-12 September, 2015.
[4]
Sridhara, K.; Biradar, G.S.; Yanamshetti, R. Subthreshold leakage power reduction in VLSI circuits: A survey. Proceedings of the International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, India, 6-8 April,2016.
[5]
Jiao, H.; Kursun, V. Threshold voltage tuning for faster activation with lower noise in tri-mode MTCMOS circuits. IEEE Transac. Very Large Scale Integr. (VLSI). Sys, 2012, 20(4), 741-745.
[6]
Jiao, H.; Kursun, V. Mode transition Timing and energy overhead analysis in noise-aware MTCMOS circuits. Microelectronics J., 2014, 45(8), 1125-1131.
[7]
Zhao, W.; Alvarez, A.B.; Ha, Y. 765-nm 25.1-ns 30.7-fJ robust subthreshold level shifter with wide conversion range (related to MTCMOS). IEEE Transac. Circuits, 2015, 62(7), 671-675.
[8]
Verma, P.; Noor, A.; Sharma, A.K.; Kumar, S.V. Power gating and its repercussions—a review. Proceedings of the IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), Delhi, India, 4-6 July 2016.
[9]
Cerqueira, J.P.; Seok, M. Temporarily fine-grained sleep technique for near- and subthreshold parallel architectures. IEEE Transac. Very Large Scale Integr. (VLSI). Sys, 2017, 25(1), 189-197.
[10]
Chen, S-H.; Lin, Y-L.; Chao, M.C-T. Power-up sequence control for MTCMOS designs. IEEE Transac. Very Large Scale Integr. (VLSI). Sys, 2013, 21(3), 413-423.
[11]
Chang, M-C.; Hsieh, M-H.; Yang, P-H. Low-power asynchronous NCL pipelines with fine-grain power gating and early sleep. IEEE Transac. Circuits Sys. II, 2014, 61(12), 957-961.
[12]
Jiao, H.; Kursun, V. Reactivation noise suppression with sleep signal slew rate modulation in MTCMOS circuits. IEEE Transac. Very Large Scale Integr. (VLSI). Sys, 2013, 21(3), 533-545.
[13]
Wang, X.; Xu, J.; Zhang, W.; Wu, X.; Ye, Y.; Wang, Z.; Nikdast, M.; Wang, Z. Actively alleviate power gating-induced power/ground noise using parasitic capacitance of on-chip memories in MPSoC. IEEE Transac. Very Large Scale Integr. (VLSI). Sys., 2015, 23(2), 266-279.
[14]
Rastogi, R.; Pandey, S. Novel design techniques for noise-tolerant power-gated circuits. J. Semiconduc., 2017, 38(1), 15001-15017.
[15]
Firdous, A.; Anand, M.; Rajan, B. Design and implementation of enhanced leakage power reduction technique in CMOS VLSI circuits. Int. J. Appl. Eng. Res., 2017, 12(2), 155-160.
[16]
Vo, H.M.; Minh, H.C. Comparative study on power gating techniques for lower power delay product, smaller power loss, faster wakeup time. EAI Endorsed Transac. Indus. Networks Intelligent Sys, 2018, 5(15), 1-6.
[17]
Pakbaznia, E.; Fallah, F. Charge recycling in power-gated CMOS circuits. IEEE Transac. Comput-Aid. Des. Integr. Circuits Sys, 2008, 27(10), 1798-1811.
[18]
Liu, Z.; Kursun, V. Charge recycling between virtual power and ground lines for low energy MTCMOS. Proc. 8th Int. Sympos. Quality Electron. Des, 2007, 17, 239-244.
[19]
Tada, A.; Notani, H. Charge recycling in MTCMOS circuits with block dividing. IECE Electron. Express, 2007, 4(18), 562-568.
[20]
Pakbaznia, E.; Fallah, F.; Pedram, M. Sizing and placement of charge recycling transistors in MTCMOS circuits. Proc. IEEE Int. Conf. Comput.-Aid. Des., 2007, 2007, 791-796.
[21]
Kim, S.; Kosonocky, S.V.; Knebel, D.R. Understanding and minimizing ground bounce during mode transition of power gating structures. Proc. Int. Symp. Low Power Electron. Devices, 2003,, 2003, 22-25.
[22]
Khandelwal, V.; Srivastava, A. Leakage control through fine grained placement and sizing of sleep transistors. IEEE Transac. Comput.-. Aid. Des. Integr. Circuits Sys, 2007, 26, 1246-1255.

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