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Nanoscience & Nanotechnology-Asia

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ISSN (Print): 2210-6812
ISSN (Online): 2210-6820

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Research Article

CNFET Based Low Power Full Adder Circuit for VLSI Applications

Author(s): Inamul Hussain* and Saurabh Chaudhury

Volume 10, Issue 3, 2020

Page: [286 - 291] Pages: 6

DOI: 10.2174/2210681209666190220122553

Price: $65

Abstract

Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime.

Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes.

Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used.

Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

Keywords: CMOS, CNFET, hybrid, full adder, low power, PDP, VLSI.

Graphical Abstract

[1]
Rabaey, J.M.; Chandrakasan, A.; Nikolic, B. Digital integrated circuits: A design perspective, 2nd ed; Pearson Education: Delhi, India, 2003.
[2]
Zimmermann, R.; Fichtner, W. Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid-State Circuits, 1997, 32(7), 1079-1090.
[3]
Radhakrishnan, D. Low-voltage low-power CMOS full adder. IEE Proc. Circuits Devices Sys., 2001, 148(1), 19-24.
[4]
Goel, S.; Kumar, A.; Bayoumi, M.A. Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Transac. Very Large Scale Integr. (VLSI). Sys, 2006, 14(12), 1309-1321.
[5]
Hussain, I.; Kumar, M. Design and performance analysis of a 3-2 compressor by using improved architecture. J. Active Passive Electr. Devices, 2017, 12(3-4), 173-181.
[6]
Phaedon, A.; Zhihong, C.; Vasili, P. Carbon-based electronics. Nat. Nanotechnol., 2007, 2(1), 605-615.
[7]
Deng, J.; Wong, H.S.P. A compact SPICE model for carbon-nanotube field-effect transistors including non-idealities and its application—Part I: Model of the intrinsic channel region. IEEE Trans. Electron Dev., 2007, 54(12), 3186-3194.
[8]
Deng, J.; Wong, H.S.P. A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking. IEEE Trans. Electron Dev., 2007, 54(12), 3195-3205.
[9]
Chang, C.H.; Gu, J.; Zhang, M. A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Transac. Very Large Scale Integr. (VLSI). Sys, 2005, 13(6), 686-695.
[10]
Vesterbacka, M. A 14-transistor CMOS full adder with full voltage- swing nodes. 1999 IEEE Workshop on Signal Processing Systems SiPS 99. Design and Implementation (Cat. No.99TH8461), Taipei, Taiwan, October. 1999, 713-722.
[11]
Bui, H.T.; Wang, Y.; Jiang, Y. Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates. IEEE Transac. Circuits Sys II Anal. Digital Signal Process, 2002, 49(1), 25-30.
[12]
Zhang, M.; Gu, J.; Chang, C-H. A novel hybrid pass logic with static CMOS output drive full-adder cell. Circuits and systems, 2003. ISCAS '03, Proceedings of the 2003 International Symposium on, Bangkok, Thailand, May. 2003, V-317-V-320.
[13]
Wang, J-M. Fang, S.-C.; Feng, W.-S. New efficient designs for XOR and XNOR functions on the transistor level. IEEE J. Solid-State Circuits, 1994, 29(7), 780-786.
[14]
Wairya, S.; Singh, G.; Nagaria, R.K.; Tiwari, S. Design analysis of XOR (4T) based low voltage CMOS full adder circuit. Nirma University International Conference on Engineering, Ahmedabad, Gujarat, India December 8-11. 2011.
[15]
Goel, S.; Elgamel, M.; Bayoumi, M.A. Novel design methodology for high-performance XOR-XNOR circuit design. Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. Sao Paulo, Brazil, September 8-11. 2003.
[16]
Bhattacharyya, P.; Kundu, B.; Ghosh, S.; Kumar, V.; Dandapat, A. ‘Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Transac. Very Large Scale Integr. (VLSI). Syst, 2015, 23(10), 2001-2008.
[17]
Stanford University: Stanford CNFET Model-HSPICE Available from:. https://nano.stanford.edu/stanford-cnfet-model

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