Login Register Cart 0
Generic placeholder image

International Journal of Sensors, Wireless Communications and Control

Editor-in-Chief

ISSN (Print): 2210-3279
ISSN (Online): 2210-3287

Back
Journal Home About Journal Editorial Board Journal Insight Current Issue Volumes/Issues
Subscribe
Research Article

High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology

Author(s): Jitendra Kumar Saini, Avireni Srinivasulu* and Renu Kumawat

Volume 9, Issue 4, 2019

Page: [462 - 467] Pages: 6

DOI: 10.2174/2210327909666190206144601

Price: $65

Abstract

Background: The advent of High Performance Computing (HPC) applications and big data applications has made it imparitive to develop hardware that can match the computing demands. In such high performance systems, the high speed multipliers are the most sought after components. A compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier, also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit design proposed here improves overall performance and efficiency of the arithmetic circuits in terms of power consumption, delay and power delay product. The proposed 5:2 compressor circuit was implemented using both CMOS and Carbon Nano Tube Field Effect Transistor (CNTFET) technologies and it was observed that the proposed circuit has yielded better results with CNTFETs as compared to MOSFETs.

Methods/Results: The proposed 5:2 compressor circuit was designed with CMOS technology simulated at 45 nm with voltage supply 1.0 V and compared it with the existing 5:2 compressor designes to validate the improvements. Thereafter, the proposed design was implemented with CNTFET technology at 32 nm and simulated with voltage supply 0.6 V. The comparision results of proposed 5:2 compressor with existing designs implemented using CMOS. The results also compare the proposed design on CMOS and CNTFET technologies for parameters like power, delay, power delay product.

Conclusion: It can be concluded that the proposed 5:2 compressor gives better results as compared to the existing 5:2 compressor designs implemeted using CMOS. The improvement in power, delay and power delay product is approx 30%, 15% and 40% respectively. The proposed circuit of 5:2 compressor is also implemented using CNTFET technology and compared, which further enhances the results by 30% (power consumption and PDP). Hence, the proposed circuit implemented using CNTFET gives substantial improvements over the existing circuits.

Keywords: Carbon nano tubes, carbon nanotube field effect transistor, CNTFET, CNTs, multi walled nanotube, MWNT, single walled nanotube, SWNT.

« Previous Next »
Graphical Abstract

[1]
Sahoo SK, Akhilesh G, Sahoo R. Design of a high performance carry generation circuit for ternary full adder using CNTFET. IEEE Int Symposium on Nanoelectronic and Info Systems (iNIS), Bhopal, 2017: pp. 46-9. DOI: 10.1109/iNIS.2017.19
[2]
Lin S, Kim YB, Lombardi F. Design of a CNTFET-based SRAM cell by dual-chirality selection. IEEE Trans Nanotechnol 2010; 9(1): 30-7. DOI: 10.1109/TNANO. 2009.2025128
[3]
Rahman F, Zaidi AM, Anam N, Akter A. Performance evaluation of a 32-nm CNT-OPAMP: Design, characteristic optimization and comparison with CMOS technology. In: 14th Int Conf Comp Info Tech Dhaka. 2011; pp. 583-8.
[http://dx.doi.org/10.1109/ICCITechn.2011.6164856]
[4]
Hoenlein W, Kreupl F, Duesberg GS, et al. Carbon nanotube applications in microelectronics. IEEE Trans Compon Packag Tech 2004; 27(4): 629-34.
[http://dx.doi.org/10.1109/ TCAPT.2004.838876]
[5]
Bardhan S, Rahaman H. Analysis of design-oriented compact model for zigzag semiconducting CNTFETs. Int Conf on Electr, Commun Instrument Kolkata, 2014; pp. 1-4. DOI:10. 1109/ICECI.2014. 6767384
[6]
Karthikeyan S, Karan Reddy MC, Monica PR. Design of CNTFET-based ternary control unit and memory for a ternary processor Int Conf Microelectr Dev, Circuits Syst (ICMDCS). Vellore 2017; pp. 1-4.
[http://dx.doi.org/10.1109/ICMDCS.2017.8211568]
[7]
Menon R, Radhakrishnan D. High performance 5:2 compressor architecture. IEEE Proc Circ Dev Syst 2006; 153(5): 447-52. DOI: 10.1049/ip-cds: 20050152
[8]
Sreehari V, Krishna MK, Avinash L, Reddy PS, Srinivas MB. Novel architectures for high-speed and low-power 3-2, 4-2 and 5-2 compressors. In 20th Int Conf on VLSI design; Bangalore, India, 2007: pp. 324-9, DOI: 10.1109/ VLSID.2007.116.
[9]
Tohidi M, Mousazadeh M, Akbari S, Hadidi K, Khoei A. CMOS implementation of a new high speed, glitch-free 5-2 compressor for fast arithmetic operations. In Proc 20th Int Conf Mixed Design Integrat Circuits Syst - MIXDES Gdynia, 2013: pp. 204-8.
[10]
Najafi A, Timarchi S, Najafi A. High-speed energy-efficient 5:2 compressor. 37th Int Convent Info Commun Tech, Electr Microelectr Opatija, Croatia, 2014; pp. 80-4. DOI: 10.1109/MIPRO. 2014.6859537.
[11]
Najafi A, Najafi A, Mirzakuchaki S. Low-power and highperformance 5:2 compressors.22nd Iranian Conf Electr Engr. Tehran, Iran. 2014; pp. 33-7.
[http://dx.doi.org/10.1109/IranianCEE.2014.6999498]
[12]
Balobas D, Konofaos N. Low-power high-performance CMOS 5-2 compressor with 58 transistors. Electron Lett 2018; 54(5): 278-80.
[http://dx.doi.org/10.1049/el.2017.3339]
[13]
Nishad AK, Chandel R. Analysis of low power high performance XOR gate using GDI technique Int Conf Computat Intell Commun Netwo; Gwalior, 2011; pp. 187-91. DOI: 10.1109/CICN. 2011.37
[14]
Singh NK, Sharma PK. 2T 2:1 MUX based 1 bit full adder design. Int Conf Commun Signal Process, Melmaruvathur, 2014; pp. 1491- 3.
[http://dx.doi.org/10.1109/ICCSP.2014.6950097]
[15]
Navi K, Rashtian M, Khatir A, Keshavarzian P, Hashemipour O. High speed capacitor-inverter based carbon nanotube full adder Nanoscale Res Lett 2010; 5(5): 859-62. DOI: 10. 1007/s11671- 010-9575-4.
[16]
Lakshmi PV, Sarada M, Srinivasulu A, Pal D. Three novel singlestage full swing 3-input XOR. Int J Electr 2018; 105(8): 1416-32. https://doi.org/10.1080/00207217. 2018. 1460767.
[17]
Sarada M, Srinivasulu A, Pal D. Novel low-supply, differential XOR/ XNOR with rail-to-rail swing, for hamming-code generation. Int J Electr Lett 2018; 6(3): 272-87.
[18]
Saini JK, Srinivasulu A, Singh BP. A new low-power full-adder cell for low voltage using CNTFETs. In: Proc IEEE Int Conf Electr, Comp Artif Intell 2017 July 29; Targoviste, Romania, pp. 6.
[http://dx.doi.org/10.1109/ECAI.2017.8166425.]
[19]
Kavitha P, Sarada M, Vijayavardhan K, Sudhavani Y, Srinivasulu A. Carbon nano tube field effect transistors based ternary Ex-OR and Ex-NOR gates Curr Nanosci 2016; 12(4): 1-7. 2016.
[http://dx.doi.org/10.2174/1573413712666151216221629]

Rights & Permissions Print Cite
Article Metrics
13
2
© 2024 Bentham Science Publishers | Privacy Policy