Copper Metallization for Current Very Large Scale Integration

Q.      Jiang; Y.      F. Zhu; M.      Zhao

doi:10.2174/187221011795909152

Abstract

As silicon technology scaling progresses to the 32 nm node or even further, the design on the propagation of electromagnetic signals becomes increasingly appealing due to their unyielding constraints on interconnect delay. Because of its high conductivity and electromigration resistance, Cu is now the interconnect materials in current VLSI. To ensure the signal propagation via the Cu interconnects upon the increasingly reduction in the interconnect width, related issues on Cu interconnects, such as electron scattering at surfaces and grain boundaries, electromigration failure and surface oxidation, still need to be further understood and addressed. Besides this, the performance of low-k dielectrics and reliable barrier structures, which are also much important among the device parts, are required to be further improved to minimize the signal delay and to prevent penetration of different materials, respectively. On the basis of the paper published at Recent Patents on Nanotechnology 2007;1:193-209, this review will focus on recent patents and some studies on Cu metallization including Cu interconnect wires, low-k dielectrics and related barrier materials as well as manufacturing techniques in VLSI, which are one of the most essential concerns in microelectronic industry and decide further development of VLSI. This review will benefit for the design of the Cu metallization in the current VLSI.

Keywords: Cu interconnects, low-k dielectrics, barrier structure, very large scale integration, Copper Metallization, Large Scale Integration, microelectronics, velocity of electromagnetic waves, Interconnect technology, electromigration, electrical parameters, diffusion progress, Electrical Resistivity, Oxidation Resistance, CMP Process, Thermal Annealing Process, Surface Treatment Process