Generic placeholder image

Recent Advances in Electrical & Electronic Engineering

Editor-in-Chief

ISSN (Print): 2352-0965
ISSN (Online): 2352-0973

Research Article

Study of the Reliability for the Leakage Mitigation Methods using FinFETs

Author(s): Kajal and Vijay Kumar Sharma*

Volume 16, Issue 7, 2023

Published on: 28 April, 2023

Page: [697 - 708] Pages: 12

DOI: 10.2174/2352096516666230414134447

Price: $65

Abstract

Introduction: In the very large-scale integration (VLSI) industry, scaling plays an important role in providing compact size and high-speed digital circuits. The major drawbacks faced by logic circuits are power dissipation and process, voltage, and temperature (PVT) variations. In the VLSI industry, the prediction of variability tolerance capability is mandatory to know the future performance of the circuits. The impact of PVT variation is large in nanoscale logic circuits and it has the power to alter the output characteristics of any logic circuit. The reasons that cause PVT variations are manufacturing defects, environmental conditions, and mishandling issues.

Aims and Objective: This paper aims to discuss the process variations and briefly describe the previous work related to variability and various factors involved in PVT simulations. It also provides the idea of Monte-Carlo simulation in the Cadence Virtuoso tool.

Methods: In this paper, the impact of PVT variations on different fin-shaped field effect transistor (FinFET) circuits was evaluated using the Cadence Virtuoso tool. Monte-Carlo simulation was performed on various leakage reduction techniques for the domino logic with the help of a multi-gate predictive technology model (PTM) FinFET at a 16nm technology node.

Results: The footer-less domino logic (FLDL) circuit is designed and simulated using different leakage reduction techniques for reliability analysis.

Conclusion: Cascaded leakage control transistor (CLCT) approach shows 81.75%, 67.83%, and 51.25% less statistical mean value for power dissipation as compared to conventional, on-off logic (ONOFIC), and alternative ONOFIC approaches in the case of FLDL OR2 logic circuit, respectively.

Graphical Abstract

[1]
M. Alioto, "Analysis of layout density in FinFET standard cells and impact of fin technology," Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 2010, pp. 3204-3207.
[http://dx.doi.org/10.1109/ISCAS.2010.5537930]
[2]
G.E. Moore, "Progress in digital integrated electronics Technical literaiture, Copyright 1975 IEEE. Reprinted, with permission. Technical Digest", Int. Electron Devices Meet, vol. 11. 2006. pp.11pp. 36-13-37.
[3]
V.K. Sharma, "A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime", Aust. J. Electr. Electron. Eng., vol. 18, no. 4, pp. 217-236, 2021.
[http://dx.doi.org/10.1080/1448837X.2021.1966957]
[4]
S-M. Kang, and Y. Leblebici, CMOS Digital Integrated Circuits Analysis and Design., 3rd ed McGraw Hill Higher Education: Maidenhead, England, 2003.
[5]
A. Razavieh, P. Zeitzoff, and E.J. Nowak, "Challenges and limitations of CMOS scaling for FinFET and beyond architectures", IEEE Trans. Nanotechnol., vol. 18, pp. 999-1004, 2019.
[http://dx.doi.org/10.1109/TNANO.2019.2942456]
[6]
"Chenming Hu, J. Bokor, Tsu-Jae King, E. Anderson, C. Kuo, K. Asano, H. Takeuchi, J. Kedzierski, Wen-Chin Lee, and D. Hisamoto, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm”", IEEE Trans. Electron Dev., vol. 47, no. 12, pp. 2320-2325, 2000.
[http://dx.doi.org/10.1109/16.887014]
[7]
V.K. Sharma, M. Pattanaik, and B. Raj, "INDEP approach for leakage reduction in nanoscale CMOS circuits", Int. J. Electron., vol. 102, no. 2, pp. 200-215, 2015.
[http://dx.doi.org/10.1080/00207217.2014.896042]
[8]
V.K. Sharma, and M. Pattanaik, "Design of low leakage variability aware ONOFIC CMOS standard cell library", J. Circuits Syst. Comput., vol. 25, no. 11, p. 1650134, 2016.
[http://dx.doi.org/10.1142/S0218126616501346]
[9]
M. Alioto, and G. Palumbo, "“Impact of supply voltage variations on full adder delay: Analysis and comparison”, IEEE Trans. Very Large Scale Integr. (VLSI)", Syst., vol. 14, no. 12, pp. 1322-1335, 2006.
[http://dx.doi.org/10.1109/TVLSI.2006.887809]
[10]
Kajal, and V.K. Sharma, "FinFET: A beginning of non-planar transistor era", In: Energy Systems in Electrical Engineering.. Springer Singapore: Singapore, 2020, pp. 139-159.
[11]
L. Bagheriye, S. Toofan, R. Saeidi, and F. Moradi, "Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing", Integration, vol. 65, pp. 128-137, 2019.
[http://dx.doi.org/10.1016/j.vlsi.2018.11.011]
[12]
A.L. Zimpeck, C. Meinhardt, and R.A.L. Reis, "Impact of PVT variability on 20 nm FinFET standard cells", Microelectron. Reliab., vol. 55, no. 9-10, pp. 1379-1383, 2015.
[http://dx.doi.org/10.1016/j.microrel.2015.06.039]
[13]
A.L. Zimpeck, C. Meinhardt, L. Artola, G. Hubert, F.L. Kastensmidt, and R.A.L. Reis, "Impact of different transistor arrangements on gate variability", Microelectron. Reliab., vol. 88-90, pp. 111-115, 2018.
[http://dx.doi.org/10.1016/j.microrel.2018.06.090]
[14]
A.L. Zimpeck, C. Meinhardt, G. Posser, and R. Reis, "FinFET cells with different transistor sizing techniques against PVT variations," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada, 2016, pp. 45-48.
[http://dx.doi.org/10.1109/ISCAS.2016.7527166]
[15]
A. Tang, Y. Yang, C.Y. Lee, and N.K. Jha, "“McPAT-PVT: Delay and power modeling framework for FinFET processor architectures under PVT variations”, IEEE Trans. Very Large Scale Integr. (VLSI)", Syst., vol. 23, no. 9, pp. 1616-1627, 2015.
[http://dx.doi.org/10.1109/TVLSI.2014.2352354]
[16]
S. Ilin, D. Ryzhova, and A. Korshunov, "Comparative analysis of standard cells performance for 7 nm FinFET and 28 nm CMOS technologies with considering for parasitic elements," 2018 IEEE Conference of russian young researchers in electrical and electronic engineering (EIConRus), moscow and St. Petersburg, Russia, 2018, pp. 1360-1363.
[http://dx.doi.org/10.1109/EIConRus.2018.8317349]
[17]
"Kajal, and V.K. Sharma, “Design and simulation for NBTI aware logic gates”", Wirel. Pers. Commun., vol. 120, no. 2, pp. 1525-1542, 2021.
[http://dx.doi.org/10.1007/s11277-021-08522-z]
[18]
O. Stramer, "Monte carlo statistical methods", J. Am. Stat. Assoc., vol. 96, no. 453, pp. 339-355, 2001.
[http://dx.doi.org/10.1198/jasa.2001.s372]
[19]
C. Jacoboni, P. Lugli, Eds., The Monte Carlo method for semiconductor device simulation., Springer My Copy: UK, 1989.
[http://dx.doi.org/10.1007/978-3-7091-6963-6]
[20]
U. Mushtaq, and V.K. Sharma, "Design and analysis of INDEP FinFET SRAM cell at 7‐nm technology", Int. J. Numer. Model., vol. 33, no. 5, p. e2730, 2020.
[http://dx.doi.org/10.1002/jnm.2730]
[21]
V.K. Sharma, M. Pattanaik, and B. Raj, "PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits", Microelectron. Reliab., vol. 54, no. 1, pp. 90-99, 2014.
[http://dx.doi.org/10.1016/j.microrel.2013.09.018]
[22]
S. Garg, and T.K. Gupta, "“Low power domino logic circuits in deep-submicron technology using CMOS”, Eng. Sci. Techn", Int. J., vol. 21, no. 4, pp. 625-638, 2018.
[http://dx.doi.org/10.1016/j.jestch.2018.06.013]
[23]
V.K. Sharma, M. Pattanaik, and B. Raj, "ONOFIC approach: Low power high speed nanoscale VLSI circuits design", Int. J. Electron., vol. 101, no. 1, pp. 61-73, 2014.
[http://dx.doi.org/10.1080/00207217.2013.769186]
[24]
V.K. Sharma, and M. Pattanaik, "A reliable ground bounce noise reduction technique for nanoscale CMOS circuits", Int. J. Electron., vol. 102, no. 11, pp. 1852-1866, 2015.
[http://dx.doi.org/10.1080/00207217.2014.996786]
[25]
"Kajal, and V.K. Sharma, “A novel low power technique for FinFET domino OR logic”", J. Circuits Syst. Comput., vol. 30, no. 7, p. 2150117, 2021.
[http://dx.doi.org/10.1142/S0218126621501176]
[26]
S. Garg, and T.K. Gupta, "A new technique for designing low-power high-speed domino logic circuits in FinFET technology", J. Circuits Syst. Comput., vol. 28, no. 10, p. 1950165, 2019.
[http://dx.doi.org/10.1142/S0218126619501652]
[27]
S. Garg, and T.K. Gupta, "FDSTDL: Low‐power technique for FinFET domino circuits", Int. J. Circuit Theory Appl., vol. 47, no. 6, pp. 917-940, 2019.
[http://dx.doi.org/10.1002/cta.2627]

Rights & Permissions Print Cite
© 2024 Bentham Science Publishers | Privacy Policy