Abstract
Background: For high computation, parallel and distributed processing chip multiprocessors are widely used. In chip multiprocessors, large on chip cache memories are used for performance improvement and speedy execution of the task. These cache memories consume 13% to 45% of the overall power consumed by the entire chip. As chip size shrinks with technology scaling, static energy consumed by the chip increases. This results in heating and chip malfunctioning. To solve this problem we apply static energy reduction techniques to Last Level Cache (LLC) to reduce static energy consumption and thereby chip temperature rise.
Methods: Static energy reduction is achieved with two methods. DIM_OLY_SEL Policy: In this policy, static Energy Reduction is achieved by dimming cache banks.
DIM_DARK_PAT Policy: In this method, dimming as well as darkening techniques are used to save static energy and thereby, temperature reduction.
Results: With the implementation of DIM_OLY_SEL policy LLC, Temperature Reduction up to 1.4 Kelvin, improvements in EDP (Energy Delay Product) gains up to 28% and leakage energy Saving up to 23% is observed.
With the implementation of DIM_DARK_PAT, we observed LLC temperature reduction up to 4.7 Kelvin, EDP gain improvement of 33 % and leakage energy saving 23%.
Conclusion: DIM_OLY_SEL and DIM_DARK_PAT Policies are observed to be very effective policies for energy saving and chip temperature reduction. Hence, they can be used effectively for safe chip multiprocessor functioning.
Keywords: Dark silicon, leakage energy, chip temperature, last level cache (LLC), chip multiprocessor, dim silicon.
Graphical Abstract
[1]
A.K. Coskun, T.S. Rosing, and K. Whisnant, "Temperature aware task scheduling in MPSoCs", 2007 Des. Autom. Test Eur. Conf. Exhib., p. pp. 1-6, 2007, .
[http://dx.doi.org/10.1109/DATE.2007.364540]
[http://dx.doi.org/10.1109/DATE.2007.364540]
[2]
A.K. Coskun, T.S. Rosing, and K.C. Gross, "Proactive temperature balancing for low cost thermal management in MPSoCs, In", 2008 IEEE/ACM International Conference on Computer-Aided Design, 10-13 Nov, 2008, San Jose, CA: USA, p. 2008, pp. 250-257, .
[http://dx.doi.org/10.1109/ICCAD.2008.4681582]
[http://dx.doi.org/10.1109/ICCAD.2008.4681582]
[3]
W. Liu, J. Yi, M. Li, P. Chen, and L. Yang, "Energy-efficient application mapping and scheduling for lifetime guaranteed MPSoCs", IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., vol. 38, no. 1, pp. 1-14, 2019.
[http://dx.doi.org/10.1109/TCAD.2018.2801242]
[http://dx.doi.org/10.1109/TCAD.2018.2801242]
[4]
A. Mirtar, S. Dey, and A. Raghunathan, "Joint work and voltage/frequency scaling for quality-optimized dynamic thermal management", IEEE Trans. Very Large Scale Integr.Syst., vol. 23, no. 6, pp. 1017-1030, 2015.
[http://dx.doi.org/10.1109/TVLSI.2014.2333741]
[http://dx.doi.org/10.1109/TVLSI.2014.2333741]
[5]
N. Goulding-Hotta, J. Sampson, G. Venkatesh, S. Garcia, J. Auricchio, P. Huang, M. Arora, S. Nath, V. Bhatt, J. Babb, S. Swanson, and M. Taylor, "The greendroid mobile application processor: An architecture for silicon’s dark future", IEEE Micro, vol. 31, no. 2, pp. 86-95, 2011.
[http://dx.doi.org/10.1109/MM.2011.18]
[http://dx.doi.org/10.1109/MM.2011.18]
[6]
Y. Turakhia, B. Raghunathan, S. Garg, and D. Marculescu, "HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors, In", 2013 50th ACM/EDAC/IEEE Design Automation
Conference (DAC), 29 May-7 June 2013, Austin, TX,
USA, p. 2013, pp. 1-7, .
[http://dx.doi.org/10.1145/2463209.2488948]
[http://dx.doi.org/10.1145/2463209.2488948]
[7]
C. Bienia, S. Kumar, J.P. Singh, and K. Li, "The PARSEC benchmark suite: Characterization and architectural implications In", Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 25 Oct, 2008, Toronto, Ontario, Canada, pp. 81-81, 2008.
[http://dx.doi.org/10.1145/1454115.1454128]
[http://dx.doi.org/10.1145/1454115.1454128]
[8]
S. Mittal, "A survey of architectural techniques for improving cache power efficiency", Sustain. Comput. Informatics Syst., vol. 4, no. 1, pp. 33-43, 2014.
[http://dx.doi.org/10.1016/j.suscom.2013.11.001]
[http://dx.doi.org/10.1016/j.suscom.2013.11.001]
[9]
K. Flautner, N.S. Kim, S. Martin, D. Blaauw, and T. Mudge, "“Drowsy caches: Simple techniques for reducing leakage power”, ACM SIGARCH", Comput. Archit. News, vol. 30, no. 2, pp. 148-157, 2002.
[http://dx.doi.org/10.1145/545214.545232]
[http://dx.doi.org/10.1145/545214.545232]
[10]
D. Apalkov, A. Khvalkovskiy, S. Watts, V. Nikitin, X. Tang, D. Lottis, K. Moon, X. Luo, E. Chen, A. Ong, A. Driskill-Smith, and M. Krounbi, "Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM)", ACM J. Emerg. Technol. Comput. Syst., vol. 9, no. 2, pp. 1-35, 2013.
[http://dx.doi.org/10.1145/2463585.2463589]
[http://dx.doi.org/10.1145/2463585.2463589]
[11]
H. Kim, S. Youn, and J. Kim, "Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches", J. Systems Archit., vol. 55, no. 10-12, pp. 446-456, 2009.
[http://dx.doi.org/10.1016/j.sysarc.2009.09.003]
[http://dx.doi.org/10.1016/j.sysarc.2009.09.003]
[12]
A. Raghavan, Y. Luo, A. Chandawalla, M. Papaefthymiou, K.P. Pipe, T.F. Wenisch, and M.M. Martin, "Computational sprinting, In", 2012 IEEE International Symposium on High-Performance
Comp Architecture, 25-29 Feb, 2012, New Orleans, LA, USA, p. 2012, pp. 1-12, .
[http://dx.doi.org/10.1109/HPCA.2012.6169031]
[http://dx.doi.org/10.1109/HPCA.2012.6169031]
[13]
J. Zhan, Y. Xie, and G. Sun, "NoC-sprinting: Interconnect for finegrained sprinting in the dark silicon era, In", Proceedings of the 51st Annual Design Automation Conference, 1 Jun, 2014, San Francisco, CA, USA, p. 2014, pp. 1-6, .
[http://dx.doi.org/10.1145/2593069.2593165]
[http://dx.doi.org/10.1145/2593069.2593165]
[14]
B. Gomatheeshwari, and J. Selvakumar, "Appropriate allocation of workloads on performance asymmetric multicore architectures via deep learning algorithms", Microprocess. Microsyst., p. vol. 73, pp. 102996, 2020, .
[http://dx.doi.org/10.1016/j.micpro.2020.102996]
[http://dx.doi.org/10.1016/j.micpro.2020.102996]
[15]
A.V. Umdekar, A. Nath, S. Das, and H.K. Kapoor, "Dynamic thermal management by using task migration in conjunction with frequency scaling for chip multiprocessors In", 2018 31st Int. Conf. VLSI Des. 2018 17th Int. Conf. Embed. Syst, p. 2018pp. 31-36, .
[http://dx.doi.org/10.1109/VLSID.2018.33]
[http://dx.doi.org/10.1109/VLSID.2018.33]
[16]
J. Kong, S.W. Chung, and K. Skadron, "Recent thermal management techniques for microprocessors", ACM Comput. Surv., vol. 44, no. 3, pp. 1-42, 2012.
[http://dx.doi.org/10.1145/2187671.2187675]
[http://dx.doi.org/10.1145/2187671.2187675]
[17]
H. Khdr, S. Pagani, M. Shafique, and J. Henkel, "Thermal constrained
resource management for mixed ILP-TLP workloads in
dark silicon chips In", 2015 52nd ACM/EDAC/IEEE Design Automation
Conference (DAC), 8-12 June, 2015, San Francisco, CA,
USA, p. 2015, pp. 1-6, .
[http://dx.doi.org/10.1145/2744769.2744916]
[http://dx.doi.org/10.1145/2744769.2744916]
[18]
G. Sun, H. Yang, and Y. Xie, "Performance/thermal-aware design of 3D-stacked L2 caches for CMPs", ACM Trans. Des. Autom. Electron. Syst., vol. 17, no. 2, pp. 1-20, 2012.
[http://dx.doi.org/10.1145/2159542.2159545]
[http://dx.doi.org/10.1145/2159542.2159545]
[19]
H. Noori, M. Goudarzi, K. Inoue, and K. Murakami, "Improving energy efficiency of configurable caches via temperature-aware configuration selection In", 2008 IEEE Computer Society Annual
Symposium on VLSI, 7-9 Apr, 2008, Montpellier, France, p. 2008, pp.
363-368, .
[http://dx.doi.org/10.1109/ISVLSI.2008.24]
[http://dx.doi.org/10.1109/ISVLSI.2008.24]
[20]
S. Chakraborty, and H.K. Kapoor, "Analysing the role of last level caches in controlling chip temperature", IEEE Trans. Sustain. Comput., vol. 3, no. 4, pp. 289-305, 2018.
[http://dx.doi.org/10.1109/TSUSC.2018.2823542]
[http://dx.doi.org/10.1109/TSUSC.2018.2823542]
[21]
B. Salami, M. Baharani, and H. Noori, "Proactive task migration with a self-adjusting migration threshold for dynamic thermal management of multi-core processors", J. Supercomput., vol. 68, no. 3, pp. 1068-1087, 2014.
[http://dx.doi.org/10.1007/s11227-014-1140-y]
[http://dx.doi.org/10.1007/s11227-014-1140-y]
[22]
H. Mizunuma, Y.C. Lu, and C.L. Yang, "Thermal coupling aware task migration using neighboring core search for many-core systems In", 2013 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), 22-24 April, 2013, Hsinchu, Taiwan, p. 2013, pp. 1-4, .
[http://dx.doi.org/10.1109/VLDI-DAT.2013.6533805]
[http://dx.doi.org/10.1109/VLDI-DAT.2013.6533805]
[23]
L. Li, "Leakage energy management in cache hierarchies In", Proceedings International Conference on Parallel Architectures and Compilation Techniques, 25-25 Sept, 2002, Charlottesville, VA, USA, p. 2002, pp. 131-140, .
[http://dx.doi.org/10.1109/PACT.2002.1106012]
[http://dx.doi.org/10.1109/PACT.2002.1106012]
[24]
A. Bartolini, M. Cacciari, A. Tilli, and L. Benini, "Thermal and energy management of high-performance multicores: Distributed and self-calibrating model-predictive controller", IEEE Trans. Parallel Distrib. Syst., vol. 24, no. 1, pp. 170-183, 2012.
[http://dx.doi.org/10.1109/TPDS.2012.117]
[http://dx.doi.org/10.1109/TPDS.2012.117]
[25]
M. Shafique, and S. Garg, "Computing in the dark silicon era: Current trends and research challenges", IEEE Des. Test, vol. 34, no. 2, pp. 8-23, 2017.
[http://dx.doi.org/10.1109/MDAT.2016.2633408]
[http://dx.doi.org/10.1109/MDAT.2016.2633408]
[26]
M. Li, W. Liu, L. Yang, P. Chen, and C. Chen, "Chip temperature optimization for dark silicon many-core systems", IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., vol. 37, no. 5, pp. 941-953, 2018.
[http://dx.doi.org/10.1109/TCAD.2017.2740306]
[http://dx.doi.org/10.1109/TCAD.2017.2740306]
[27]
A. Bardine, P. Foglia, G. Gabrielli, and C.A. Prete, "Analysis of static and dynamic energy consumption in NUCA caches: Initial results In", Proceedings of the 2007 Workshop on Memory Performance
Dealing with Applications System and Architecture, 16 Sept,
2007, Brasov, Romania, p. 2007, pp. 105-112, .
[http://dx.doi.org/10.1145/1327171.1327184]
[http://dx.doi.org/10.1145/1327171.1327184]
[28]
N. Muralimanohar, R. Balasubramonian, and N.P. Jouppi, CACTI 6.0: A tool to understand large caches., Univ. Utah Hewlett Packard Lab. Tech. Rep vol. 147, 2009.
[29]
N. Binkert, "The gem5 simulator", In: ACM SIGARCH Comput. Arch. news, p. vol. 39, no. 2, pp. 1-7, 2011.
[http://dx.doi.org/10.1145/2024716.2024718]
[http://dx.doi.org/10.1145/2024716.2024718]
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