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Micro and Nanosystems

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ISSN (Print): 1876-4029
ISSN (Online): 1876-4037

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Review Article

Fast Complete Ternary Addition with Novel 3:1 T-Multiplexer

Author(s): Aloke Saha*, Rahul Pal, Tripti Kumari, Rakesh K. Singh, Somashree Chakraborty and Jayanta Ghosh

Volume 14, Issue 4, 2022

Published on: 25 May, 2022

Page: [304 - 313] Pages: 10

DOI: 10.2174/1876402914666220425124154

Price: $65

Abstract

Background: Complete Ternary Adder is the prime building block for Ternary Carry Save Adder (TCSA) and acts as a critical deciding factor to optimize the overall speed-power performance for many complex ternary computing like ternary multiplications.

Objective: This work proposes a new idea for high-speed complete Ternary Adder design with reduced Power-Delay-Product (PDP) using PTL (Pass Transistor Logic) based novel 3:1 Ternary Multiplexer (T-MUX) for efficient ternary computing.

Methods: In the proposed approach, a novel 3:1 T-MUX with conventional E-MOS (Enhancementtype Metal Oxide Semiconductor) transistor is designed first. The Novel Select Unit (SU) and Control Unit (CU) are the prime building blocks of the proposed T-MUX circuit, which are discussed in detail. The 3:1 T-MUX is exploited next to achieve the proposed high-speed, low-PDP Ternary Half and Full Adder operation. The complete adder circuit is designed and optimized based on BSIM4 device parameters using 32nm standard CMOS technology with 1.0V supply rail at 27°C temperature. Trit values “0”, “1” and “2” are represented with 0V, 0.5V and 1.0V respectively. Extensive T-Spice simulation with all possible test patterns using PWL (Piece Wise Linear) input source validates the proposed circuit. The evaluated speed-power result of the proposed TFA is then compared with the most recent competitive study to set a benchmark.

Results: The proposed complete TFA offers 68.9% and 82.5% reduction in propagation delay along with 27.7% and 31.6% Power-Delay-Product (PDP) reduction compared to the most recent competitive complete TFA Design-1 and Design-2, respectively.

Discussion: As per the study, the proposed idea can be a good selection to produce fast ternary addition along with reduced Power-Delay-Product (PDP).

Conclusion: The proposed complete TFA can be utilized effectively as Ternary Carry Save Adder (TCSA) for fast, low-PDP ternary multiplication as well as for other computation-intensive applications.

Keywords: Complete ternary addition, enhancement-type MOSFET, pass transistor logic, ternary multiplexing, t-spice simulation, T-MUX.

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Graphical Abstract

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