Login Register Cart 0
Generic placeholder image

Nanoscience & Nanotechnology-Asia

Editor-in-Chief

ISSN (Print): 2210-6812
ISSN (Online): 2210-6820

Back
Journal Home About Journal Editorial Board Journal Insight Current Issue Volumes/Issues
Subscribe
Research Article

Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node

Author(s): T.P. Dash*, S. Dey, S. Das, J. Jena, E. Mahapatra and C.K. Maiti

Volume 10, Issue 4, 2020

Page: [447 - 456] Pages: 10

DOI: 10.2174/2210681209666190809101307

Price: $65

Abstract

Background: In nano and microelectronics, device performance enhancement is limited by downscaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. This paper explores the key design challenges of stress-engineered FinFETs based on the epitaxial SiGe S/D at 7 nm Technology node.

Objective: To study the mechanical stress evolution in a tri-gate FinFET at 7 nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the devices through device simulation.

Methods: 3D sub-band Boltzmann transport analysis for tri-gate PMOS FinFETs was used, with 2D Schrödinger solution in the fin cross-section and 1D Boltzmann transport along the channel.

Results: Using stress maps, the mechanical stress impact on the transfer characteristics of the device through device simulation has been analyzed.

Conclusion: Suitability of predictive TCAD simulations to explore the potential of innovative strain-engineered FinFET structures for future generation CMOS technology is demonstrated.

Keywords: Strain engineering, FinFETs, SiGe, source/drain stressor design, stress tuning, TCAD, ballistic transport, driftdiffusion, quantum transport solver, Subband Boltzmann transport equation solver.

Graphical Abstract

[1]
Maiti, C.K.; Maiti, T.K. Strain-engineered MOSFETs; CRC Press: Ohio, USA, 2012. 0.
[http://dx.doi.org/10.1201/b13014]
[2]
Maiti, C.K. Introducing technology computer-aided design (TCAD); CRC Press: Ohio, USA, 2017.
[http://dx.doi.org/10.1201/9781315364506]
[3]
Intel Corporation. Intel 22nm 3-D Tri-Gate Transistor Technology. 2011. Available from: http://newsroom.intel.com/docs/DOC-2032.pdf
[4]
Maiti, C.K. Computer aided design of micro- and nanoelectronic devices; World Scietific: Singapore, 2016.
[5]
Wang, G.; Luo, J.; Qin, C.; Liang, R.; Xu, Y.; Liu, J.; Li, J.; Yin, H.; Yan, J.; Zhu, H.; Xu, J.; Zhao, C.; Radamson, H.H.; Ye, T. Integration of highly strained SiGe in source and drain with HK and MG for 22 nm bulk PMOS transistors. Nanoscale Res. Lett., 2017, 12(1), 123.
[http://dx.doi.org/10.1186/s11671-017-1908-0] [PMID: 28228008]
[6]
Dash, T.P.; Dey, S.; Das, S.; Maiti, C.K. Proceeding of ICRIEECE, SpringerSingapore2018.
[7]
Moroz, V.; Huang, J.; Choi, M. IEEE Electron Devices Technology and Manufacturing Conference (EDTM) : KL, Malaysia, 2017.
[8]
Pei, G.; Kedzierski, J.; Oldiges, P.; Ieong, M.; Kan, E.C-C. FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Trans. Electron Dev., 2002, 49, 1411-1419.
[http://dx.doi.org/10.1109/TED.2002.801263]
[9]
Wang, G.L.; Moeen, M.; Abedin, A.; Kolahdouz, M.; Luo, J.; Qin, C.L.; Zhu, H.L.; Yan, J.; Yin, H.Z.; Li, J.F.; Zhao, C.; Radamson, H.H. Optimization of SiGe selective epitaxy for source/drain engineering in 22 nm node complementary metal–oxide semiconductor (CMOS). J. Appl. Phys., 2013, 114, 2351.
[http://dx.doi.org/10.1063/1.4821238]
[10]
Yiluan, G.; Guilei, W.; Chao, Z. Simulation and characterization of stress in FinFETs using novel LKMC and nano beam diffraction methods. J. Semicond., 2015, 36, 086001-1-5.
[11]
Shur, M.S. Low ballistic mobility in submicron HEMTs. IEEE Electron Device Lett., 2002, 23, 511-513.
[http://dx.doi.org/10.1109/LED.2002.802679]
[12]
Lenzi, M.; Palestri, P.; Gnani, E.; Reggiani, S.; Gnudi, A.; Esseni, D.; Selmi, L.; Baccarani, G. Investigation of the transport properties of silicon nanowires using deterministic and Monte Carlo approaches to the solution of the Boltzmann transport equation. IEEE Trans. Electron Dev., 2008, 55, 2086-2096.
[http://dx.doi.org/10.1109/TED.2008.926230]
[13]
Luisier, M.; Schenk, A. Two-dimensional tunneling effects on the leakage current of MOSFETs with single dielectric and high-k gate stacks. IEEE Trans. Electron Dev., 2008, 55, 1494-1501.
[http://dx.doi.org/10.1109/TED.2008.922493]
[14]
Luisier, M.; Schenk, A.; Fichtner, W. Quantum transport in two and three-dimensional nanoscale transistors: Coupled mode effects in the nonequilibrium Green’s function formalism. J. Appl. Phys., 2006. 100043713
[http://dx.doi.org/10.1063/1.2244522]
[15]
Zilli, M.; Esseni, D.; Palestri, P.; Selmi, L. On the apparent mobility in nanometric n-MOSFETs. IEEE Electron Device Lett., 2007, 28, 1036-1039.
[http://dx.doi.org/10.1109/LED.2007.907553]
[16]
Gnani, E.; Gnudi, A.; Reggiani, S.; Baccarani, G. Effective mobility in nanowire FETs under quasi-ballistic conditions. IEEE Trans. Electron Dev., 2010, 57, 336-344.
[http://dx.doi.org/10.1109/TED.2009.2035545]
[17]
Kotlyar, R.; Rios, R.; Weber, C.E.; Linton, T.D.; Armstrong, M.; Kuhn, K. Distributive quasi-ballistic drift diffusion model including effects of stress and high driving field. IEEE Trans. Electron Dev., 2015, 62, 743-750.
[http://dx.doi.org/10.1109/TED.2015.2392717]
[18]
Choi, M.; Moroz, V.; Smith, L.; Huang, J. FinFET/nanowire design for 5nm/3nm technology nodes: Channel cladding and introducing a “bottleneck” shape to remove performance bottleneck. Proceeding of SISPAD, Toyama, Japan28 Feb.-2 March, 2017
[19]
Jin, S.; Hong, S-M.; Choi, W.; Lee, K-H.; Park, Y. Electron mobility in junctionless Ge nanowire NFETs. Proc. Int. Conf. Simul. Semicond. Processes Devices (SISPAD), 2013, 1, 348-351.
[20]
Auth, C.; Allen, C.; Blattner, A.; Bergstrom, D.; Brazier, M.; Bost, M.; Buehler, M.; Chikarmane, V.; Ghani, T.; Glassman, T.; Grover, R.; Han, W.; Hanken, D.; Hattendorf, M.; Hentges, P.; Heussner, R.; Hicks, J.; Ingerly, D.A. 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. Proceedings of the Symposium on VLSI Technology (VLSIT), Honolulu, HI, USAJune 12-14, 2012
[21]
Gendron-Hansen, A.; Korablev, K.; Chakarov, I.; Egley, J.; Cho, J.; Benistant, F. TCAD analysis of finfet stress engineering for CMOS technology scaling. Proceeding of SISPAD, 2015, 1, 417-420.
[22]
VictoryProcess User’s manual., 2017.
[23]
VictoryStress User’s manual., 2017.
[24]
Packan, P.; Cea, S.; Deshpande, H.; Ghani, T.; Giles, M.; Golonzka, O.; Hattendorf, M.; Kotlyar, R.; Kuhn, K.; Murthy, A.; Ranade, P.; Shifren, L.; Weber, C.; Zawadzki, K. High Performance Hi-K+ Metal gate strain enhanced transistors on (110) silicon. IEEE Int, 2008, 1, 63-66.
[25]
VictoryDevice User’s manual., 2017.
[26]
Smith, C.S. Piezoresistance effect in germanium and silicon. Phys. Rev., 1954, 94, 42-49.
[http://dx.doi.org/10.1103/PhysRev.94.42]
[27]
Kloeck, B.; DeRooij, N.F. Mechanical sensors. Semiconduct. Sens, 1994, 160-174.
[28]
Pfann, W.G.; Thurston, R.N. Semiconducting stress transducers utilizing the transverse and shear piezoresistance effects. J. Appl. Phys., 1961, 32, 2008-2019.
[http://dx.doi.org/10.1063/1.1728280]
[29]
Mason, W.P.; Thurston, R.N. Use of piezoresistive materials in the measurement of displacement, force, and torque. J. Acoust. Soc. Am., 1957, 29, 1096-1101.
[http://dx.doi.org/10.1121/1.1908710]
[30]
Love, A.E.H. A treatise on the mathematical theory of elasticity, 4th ed; Cambridge University Press: Cambridge, UK, 1944.
[31]
Manku, T.; Nathan, A. Valence energy-band structure for strained group – IV semiconductors. J. Appl. Phys., 1993, 73, 1205-1213.
[http://dx.doi.org/10.1063/1.353287]
[32]
Kanda, Y. A graphical representation of the Piezoresistance Coefficients in Silicon. IEEE Trans. Electron Dev., 1982, 29, 64-70.
[http://dx.doi.org/10.1109/T-ED.1982.20659]
[33]
MINIMOS-NT User’s manual., 2017.

Rights & Permissions Print Cite
Article Metrics
2
© 2024 Bentham Science Publishers | Privacy Policy