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International Journal of Sensors, Wireless Communications and Control

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ISSN (Print): 2210-3279
ISSN (Online): 2210-3287

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Research Article

FPGA Implementation of Vedic Squarer for Communication Systems

Author(s): Angshuman Khan*, Sudip Halder, Souvik Saha and Rajeev Arya

Volume 10, Issue 6, 2020

Page: [857 - 865] Pages: 9

DOI: 10.2174/2210327909666190611143919

Price: $65

Abstract

Background: The squarer or squaring circuit is extensively used in communication systems as a mathematical function with applications of frequency doublers, Finite Impulse Response (FIR) filters, peak amplitude detectors, digital processors and analog multipliers, etc. and especially for square law detection circuits.

Objectives: Vedic multipliers are popular mainly for their simplicity in the literature of digital multipliers.

Methods: Recently, proposed 2-bit square calculator or self-multiplier already gained the attraction of the researchers.

Results & Conclusion: In this paper, two bits squarer or self-multiplier or square calculator has been successfully coded using VHDL, verified in Xilinx tool and finally implemented in popular FPGA Spartan kit.

Keywords: ASIC, communication system, FPGA, multiplier, squarer, VHDL.

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