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ISSN (Print): 1573-4137
ISSN (Online): 1875-6786

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Review Article

A Review on the Study of Temperature Effects in the Design of A/D Circuits based on CNTFET

Author(s): Roberto Marani and Anna Gina Perri*

Volume 15, Issue 5, 2019

Page: [471 - 480] Pages: 10

DOI: 10.2174/1573413714666181009125058

Price: $65

Abstract

In this paper, we review a procedure to study the effects of temperature in the design of A/D circuits based on CNTFETs. At first, we briefly describe a compact model, already proposed by us, in which the temperature variation in the drain current equation and in energy band gap is considered. Then, the effects of temperature variations in the design of analog circuits, such as a cascode current sink mirror and an Operational Transconductance Amplifier (OTA), and in the design of digital circuits including in particular NAND and NOR logic gates, are illustrated and widely discussed.

Keywords: CNTFETs, modeling, temperature effects, analogue circuits, digital circuits, CAD, verilog-A.

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[1]
Tans, S.J.; Verschueren, A.R.; Dekker, C. Room-temperature transistor based on a single carbon nanotube. Nature, 1998, 393(6680), 49-52.
[2]
Martel, R.; Schmidt, T.; Shea, H.R.; Hertel, T.; Avouris, P. Single-and multi-wall carbon nanotube field-effect transistors. Appl. Phys. Lett., 1998, 73(17), 2447-2449.
[3]
Avouris, Z.; Chen, V.; Perebeino, V. Carbon-based electronics. Nat. Nanotechnol., 2007, 2, 605-615.
[4]
Perri, A.G.; Marani, R. CNTFET Electronics: Design Principles; Progedit: Bari, Italy, 2017.
[5]
Gelao, G.; Marani, R.; Diana, R.; Perri, A.G. A semi-empirical SPICE model for n-type conventional CNTFETs. IEEE Trans. NanoTechnol., 2011, 10, 506-512.
[6]
Marani, R.; Perri, A.G. A compact, semi-empirical model of carbon nanotube field effect transistors oriented to simulation software. Curr. Nanosci., 2011, 7, 245-253.
[7]
Marani, R.; Perri, A.G. A DC model of carbon nanotube field effect transistor for CAD applications. Int. J. Electron., 2012, 99, 427-444.
[8]
Marani, R.; Gelao, G.; Perri, A.G. Comparison of ABM SPICE library with Verilog-A for compact CNTFET model implementation. Curr. Nanosci., 2012, 8, 556-565.
[9]
Marani, R.; Gelao, G.; Perri, A.G. Modelling of carbon nanotube field effect transistors oriented to SPICE software for A/D circuit design. Microelectronics J., 2013, 44, 33-39.
[10]
Marani, R.; Perri, A.G. Analysis of CNTFETs operating in SubThreshold region for low power digital applications. ECS J. Solid State Sci. Technol., 2016, 5, M1-M4.
[11]
Marani, R.; Perri, A.G. A de-embedding procedure to determine the equivalent circuit parameters of RF CNTFETs. ECS J. Solid State Sci. Technol., 2016, 5, M31-M34.
[12]
Raychowdhury, A.; Mukhopadhyay, S.; Roy, K. A circuit-compatible model of ballistic carbon nanotube field-effect transistors. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., 2004, 23(10), 1411-1420.
[13]
Prégaldiny, F.; Lallement, C.; Kammerer, J.B. Design-oriented compact models for CNTFETs. International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006, pp. 34-39.
[14]
Prégaldiny, F.; Lallement, C.; Diange, B.; Sallese, M.; Krummenacher, M. Compact Modeling of Emerging Technologies with VHDL-AMS. In Huss, S.A. (ed).Advances in Design and Specification Languages for Embedded Systems; Dordrecht: Springer Netherlands, 2007.
[15]
Gelao, G.; Marani, R.; Pizzulli, L.; Perri, A.G. A model to improve analysis of CNTFET logic gates in Verilog-A-Part I: Static analysis. Curr. Nanosci., 2015, 11, 515-526.
[16]
Gelao, G.; Marani, R.; Pizzulli, L.; Perri, A.G. A model to improve analysis of CNTFET logic gates in Verilog-A-Part II: Dynamic analysis. Curr. Nanosci., 2015, 11, 770-783.
[17]
Marani, R.; Perri, A.G. A simulation study of analogue and logic circuits with CNTFETs. ECS J. Solid State Sci. Technol., 2016, 5, M38-M43.
[18]
Gelao, G.; Marani, R.; Perri, A.G. A comparison of temperature dependence of I-V characteristics in CNTFETs models. Curr. Nanomater., 2016, 1, 61-68.
[19]
Marani, R.; Perri, A.G. A DC thermal model of carbon nanotube field effect transistors for CAD applications. ECS J. Solid State Sci. Technol., 2016, 5, M3001-M3004.
[20]
Marani, R.; Perri, A.G. Effects of temperature dependence of energy band gap on I-V characteristics in CNTFETs models. Int. J. Nanosci., 2017, 161750009
[21]
Verilog-AMS language reference manual Version 2.2, 2014.
[22]
Lee, C-S.; Pop, E.; Franklin, A.D.; Haensch, W.; Wong, H-S.P. A compact virtual-source model for carbon nanotube field-effect transistors in the sub-10-nm regime-Part I: Intrinsic elements. IEEE Trans. Electron Dev., 2015, 62, 3061-3069.
[23]
Lee, C-S.; Pop, E.; Franklin, A.D.; Haensch, W.; Wong, H-S.P. A compact virtual-source model for carbon nanotube field-effect transistors in the sub-10-nm regime-Part II: Extrinsic elements, performance assessment, and design optimization. IEEE Trans. Electron Dev., 2015, 62, 3070-3079.
[24]
Deng, J.; Wong, H-S.P. A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region. IEEE Trans. Electron Dev., 2007, 54, 3186-3194.
[25]
Deng, J.; Wong, H-S.P. A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking. IEEE Trans. Electron Dev., 2007, 54, 3195-3205.
[26]
Gelao, G.; Marani, R.; Perri, A.G. Effects of temperature in CNTFET-based design of analog circuits. ECS J. Solid State Sci. Technol., 2018, 7(2), M16-M21.
[27]
Gelao, G.; Marani, R.; Perri, A.G. Effects of temperature in CNTFET-based design of digital circuits. ECS J. Solid State Sci. Technol., 2018, 7(3), M41-M48.
[28]
Gelao, G.; Marani, R.; Perri, A.G. Effects of temperature on switching time and power dissipation of CNTFET-based digital circuits. ECS J. Solid State Sci. Technol., 2018, 7(5), M63-M68.
[29]
Datta, S. Cambridge Studies in Semiconductor Physics and Microelectronic Engineering 3. Electronic Transport in Mesoscopic Systems; New York: Cambridge University Press, 1995.
[30]
Allen, P.E.; Holberg, D.R. CMOS Analog Circuit Design; Oxford University Press, 2013.
[31]
Kashti, V.V.; Monica, R. Performance analysis of CMOS comparator and CNTFET comparator design. Int. J. Res. Eng. Technol., 2014, 3(4), 862-866.
[32]
Perri, A.G. Fondamenti di Elettronica; Progedit: Bari, Italy, 2009.
[33]
Van der Ziel, A. Noise in Solid State Devices and CircuitsEd. Wiley, New York; , 1986.
[34]
Navid, R.; Jungemann, C.; Lee, T.H.; Dutton, R.W. High-frequency noise in nanoscale metal oxide semiconductor field effect transistors. J. Appl. Phys., 2007, 101, 124501-124509.
[35]
Betti, A.; Fiori, G.; Iannaccone, G. Shot noise suppression in quasi-one-dimensional field-effect transistors. IEEE Trans. Electron Dev., 2009, 56(9), 2137-2143.
[36]
Landauer, G.M.; Gonzalez, J.L. A compact noise model for carbon nanotube FETs. Proceedings of 2012 International Semiconductor Conference Dresden-Grenoble (ISCDG), 2012, pp. 53-56.
[37]
Huszka, Z.; Chakravorty, A. Correlated noise in bipolar transistors: Model implementation issues. Solid-State Electron., 2015, 114, 69-75.
[38]
Marani, R.; Gelao, G.; Perri, A.G. A compact noise model for C-CNTFETs. ECS J. Solid State Sci. Technol., 2017, 6(4), M44-M49.

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