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ISSN (Print): 1872-2121
ISSN (Online): 2212-4047

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Research Article

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

Author(s): Poonam Sharma, Ashwani Kumar Dubey* and Ayush Goyal

Volume 13, Issue 2, 2019

Page: [174 - 180] Pages: 7

DOI: 10.2174/1872212112666180810150357

Price: $65

Abstract

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput.

Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC.

Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing.

Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality.

Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

Keywords: ASIP, MAC, DSP, image processing, multiplier, wallace tree, modified booth, FPGA.

Graphical Abstract

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