Review of Network on Chip Architectures

Title:Review of Network on Chip Architectures

Volume: 10 Issue: 1

Author(s): Muhammad Athar Javed Sethi*, Fawnizu Azmadi Hussin and Nor Hisham Hamid

Affiliation:

• Department of Computer Systems Engineering, University of Engineering and Technology, Peshawar,Pakistan

Keywords: Network on Chip (NoC), link sharing, quality of service (QoS), fault-tolerant routing algorithms, switching techniques, buffer management.

Abstract: Background: Network on Chip (NoC) is a communication mechanism to provide scalable, modular, robust and high-performance communication for the on-chip network.

Switching Techniques: NoC brings the concept of packet switching from data to on-chip networks. The nodes are connected through point to point links using regular and irregular topologies. The packet traverses along these nodes to reach the destination using routing algorithm.

Conclusion: In this paper, NoC architectures are reviewed using different parameters, detail information is also provided for these parameters. The NoC architectures reviewed are proposed and implemented in last more than a decade.

Cite this article as:

Javed Sethi Athar Muhammad*, Hussin Azmadi Fawnizu and Hamid Hisham Nor, Review of Network on Chip Architectures, Recent Advances in Electrical & Electronic Engineering 2017; 10 (1) . https://dx.doi.org/10.2174/2352096510666170425102503

DOI https://dx.doi.org/10.2174/2352096510666170425102503	Print ISSN 2352-0965
Publisher Name Bentham Science Publisher	Online ISSN 2352-0973