High Efficiency 2.4 GHz CMOS Two Stages Class-F Power Amplifier for Wireless Transmitters

Title:High Efficiency 2.4 GHz CMOS Two Stages Class-F Power Amplifier for Wireless Transmitters

Volume: 9 Issue: 1

Author(s): Sohiful A.Z. Murad, Mohd N. Md Isa, Faizah A. Bakar and Rohana Sapawi

Affiliation:

Keywords: Cascade, class F, power added efficiency, power amplifier, wireless, output power.

Abstract: A design of CMOS class-F power amplifier (PA) at 2.4-GHz for wireless transmitters is presented. The class-F PA design is implemented by using 0.13-μm CMOS process. The proposed class-F PA employs cascade topology. The transistor’s on resistance is decreased by designing the transistors in parallel. Therefore, the efficiency is increased. The first stage is a common-source driver stage is biased in a class-AB to provide sufficient input voltage swing for the amplifier stage, while the amplifier stage is biased in cut-off region. Therefore, the transistor can operate as a switching-mode for high efficiency. The simulation results show that the power added efficiency (PAE) of 60% is obtained at 1.3 V power supply and the PA delivers 12 dBm output power. The chip area is 0.66 mm².

Cite this article as:

A.Z. Murad Sohiful, N. Md Isa Mohd, A. Bakar Faizah and Sapawi Rohana, High Efficiency 2.4 GHz CMOS Two Stages Class-F Power Amplifier for Wireless Transmitters, Recent Advances in Electrical & Electronic Engineering 2016; 9 (1) . https://dx.doi.org/10.2174/2352096509666151109205645

DOI https://dx.doi.org/10.2174/2352096509666151109205645	Print ISSN 2352-0965
Publisher Name Bentham Science Publisher	Online ISSN 2352-0973