A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis

Gennaro      Gelao; Roberto      Marani; Luciano      Pizzulli; Anna      Gina Perri

doi:10.2174/1573413711666150320231414

Abstract

In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.

Keywords: CNTFETs modelling, digital applications, noise margin, sub threshold currents.

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Current Nanoscience

Title:A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis

Volume: 11 Issue: 4

Author(s): Gennaro Gelao, Roberto Marani, Luciano Pizzulli and Anna Gina Perri

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Keywords: CNTFETs modelling, digital applications, noise margin, sub threshold currents.

Abstract: In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.

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Gelao Gennaro, Marani Roberto, Pizzulli Luciano and Gina Perri Anna, A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis, Current Nanoscience 2015; 11 (4) . https://dx.doi.org/10.2174/1573413711666150320231414

DOI https://dx.doi.org/10.2174/1573413711666150320231414	Print ISSN 1573-4137
Publisher Name Bentham Science Publisher	Online ISSN 1875-6786