Login Register Cart 0
Generic placeholder image

Current Nanoscience

Editor-in-Chief

ISSN (Print): 1573-4137
ISSN (Online): 1875-6786

Back
Journal Home About Journal Editorial Board Journal Insight Current Issue Volumes/Issues
Subscribe
Review Article

Recent Trends in Application of Memristor in Neuromorphic Computing: A Review

Author(s): Saswat Panda, Chandra Sekhar Dash* and Chinmayee Dora

Volume 20, Issue 4, 2024

Published on: 13 June, 2023

Page: [495 - 509] Pages: 15

DOI: 10.2174/1573413719666230516151142

Price: $65

Abstract

Recently memristors have emerged as a form of nonvolatile memory that is based on the principle of ion transport in solid electrolytes under the impact of an external electric field. It is perceived as one of the key elements to building next-generation computing systems owing to its peculiar resistive switching characteristics. The switching mechanism in a memristor is mainly governed by filamentary conduction. Further, it can be employed as a memory as well as a logic element, which makes it an ideal candidate for building innovative computer architecture. Moreover, it is capable of mimicking the characteristics of biological synapses, which makes it an ideal candidate for developing a Neuromorphic system. In this review to begin with the switching mechanism of the memristor, primarily focusing on filamentary conduction, is discussed. Few SPICE models of memristor are reviewed, and their critical comparison is performed, which are widely used to build computing systems. An in-depth study on the various crossbar memory architecture augmented with memristors is reviewed. Finally, the application of memristors in neuromorphic computing and hardware implementation of Artificial Neural Networks (ANN) employing memristors is discussed.

« Previous Next »
Graphical Abstract

[1]
Li, Y.; Wang, Z.; Midya, R.; Xia, Q.; Yang, J.J. Review of memristor devices in neuromorphic computing: Materials sciences and device challenges. J. Phys. D Appl. Phys., 2018, 51(50), 503002.
[http://dx.doi.org/10.1088/1361-6463/aade3f]
[2]
(a) Kvatinsky, S.; Satat, G.; Wald, N.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. Memristor-based material implication (IMPLY) logic: Design principles and methodologies. IEEE Trans. Very Large Scale Integr. (VLSI). Syst., 2014, 22(10), 2054-2066.;
(b) Kvatinsky, S.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. The desired memristor for circuit designers. IEEE Circuits Syst. Mag., 2013, 13(2), 17-22.
[3]
Sun, L.; Li, S.; Sun, C.; Liu, H. An axonal model for analysis of ionic concentration alterations induced by high frequency electrical stimulations. 9th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI), 15-17 October 2016 Datong, China 2016.
[http://dx.doi.org/10.1109/CISP-BMEI.2016.7852986]
[4]
Bertaud, T.; Walczyk, D.; Walczyk, C.; Kubotsch, S.; Sowinska, M.; Schroeder, T.; Wenger, C.; Vallée, C.; Gonon, P.; Mannequin, C.; Jousseaume, V.; Grampeix, H. Resistive switching of HfO2-based metal–insulator–metal diodes: Impact of the top electrode material. Thin Solid Films, 2012, 520(14), 4551-4555.
[http://dx.doi.org/10.1016/j.tsf.2011.10.183]
[5]
Chen, P.H.; Lin, C.Y.; Chang, T.C. An Ultra energy-saving metal/insulator/metal structure for one selector-one RRAM. 2020 IEEE International Interconnect Technology Conference (IITC), 05-08 October 2020 San Jose, CA, USA 2020.
[http://dx.doi.org/10.1109/IITC47697.2020.9515631]
[6]
Lin, Y.H.; Wang, C.H.; Lee, M.H.; Lee, D.Y.; Lin, Y.Y.; Lee, F.M.; Lung, H.L.; Wang, K.C.; Tseng, T.Y.; Lu, C.Y. Performance impacts of analog ReRAM non-ideality on neuromorphic computing. IEEE Trans. Electron Dev., 2019, 66(3), 1289-1295.
[http://dx.doi.org/10.1109/TED.2019.2894273]
[7]
Shahar, K.; Dmitry, B.; Slavik, L.; Guy, S.; Nimrod, W. MAGIC—memristor-aided logic. IEEE Trans. Circuits Syst. II Express Briefs, 2014, 61(11), 895-899.
[8]
Bhushan, B. Introduction to nanotechnology. In: Springer handbook of nanotechnology; , 2017.
[9]
Meena, J.S.; Sze, S.M.; Chand, U.; Tseng, T.Y. Overview of emerging nonvolatile memory technologies. Nanoscale Res. Lett., 2014, 9(1), 526.
[http://dx.doi.org/10.1186/1556-276X-9-526] [PMID: 25278820]
[10]
Patterson, D.A.; Sequin, C.H. Design considerations for single-chip computers of the future. IEEE J. Solid-State Circuits, 1980, 15(1), 44-52.
[http://dx.doi.org/10.1109/JSSC.1980.1051337]
[11]
Atabaki, A.H.; Moazeni, S.; Pavanello, F.; Gevorgyan, H.; Notaros, J.; Alloatti, L.; Wade, M.T.; Sun, C.; Kruger, S.A.; Meng, H.; Al Qubaisi, K.; Wang, I.; Zhang, B.; Khilo, A.; Baiocco, C.V. Popović M.A.; Stojanović V.M.; Ram, R.J. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip. Nature, 2018, 556(7701), 349-354.
[http://dx.doi.org/10.1038/s41586-018-0028-z] [PMID: 29670262]
[12]
Bunnam, T.; Soltan, A.; Sokolov, D.; Maevsky, O.; Yakovlev, A. Toward designing thermally-aware memristance decoder. IEEE TCAS-I, 2019, 66(11), 4337-4347.
[http://dx.doi.org/10.1109/TCSI.2019.2925021]
[13]
Suzuki, H.; Shimakawa, H.; Kumada, A.; Sato, M. Molecular dynamics study of ionic conduction in epoxy resin. IEEE Trans. Dielectr. Electr. Insul., 2022, 29(1), 170-177.
[http://dx.doi.org/10.1109/TDEI.2022.3148462]
[14]
Talati, N.; Gupta, S.; Mane, P.; Kvatinsky, S. Logic design within memristive memories using memristor-aided loGIC (MAGIC). IEEE Trans. Nanotechnol., 2016, 15(4), 635-650.
[http://dx.doi.org/10.1109/TNANO.2016.2570248]
[15]
Maffezzoni, P.; Bahr, B.; Zhang, Z.; Daniel, L. Analysis and design of boolean associative memories made of resonant oscillator arrays. IEEE Trans. Circuits Syst. I Regul. Pap., 2016, 63(11), 1964-1973.
[http://dx.doi.org/10.1109/TCSI.2016.2596300]
[16]
Wang, K.L.; Alzate, J.G.; Khalili Amiri, P. Low-power non-volatile spintronic memory: STT-RAM and beyond. J. Phys. D Appl. Phys., 2013, 46(7), 074003.
[http://dx.doi.org/10.1088/0022-3727/46/7/074003]
[17]
Lee, S.H.; Jung, Y.; Agarwal, R. Highly scalable non-volatile and ultra-low-power phase-change nanowire memory. Nat. Nanotechnol., 2007, 2(10), 626-630.
[http://dx.doi.org/10.1038/nnano.2007.291] [PMID: 18654387]
[18]
Ping, W.X.; Ying, W.Z.; Yi, S. A high reliable design of memristor-based multilevel memory. 34th Chinese Control Conference (CCC), 28-30 July 2015Hangzhou, China2015.
[http://dx.doi.org/10.1109/ChiCC.2015.7260517]
[19]
Xu, C.; Dong, X.; Jouppi, N.P.; Xie, Y. Design implications of memristor-based RRAM cross-point structures. In: Design, Automation & Test in Europe; 14-18 March 2011Grenoble, France, 2011.
[20]
Bae, W.; Yoon, K.J. Comprehensive read margin and BER analysis of one selector-one memristor crossbar array considering thermal noise of memristor with noise-aware device model. IEEE Trans. Nanotechnol., 2020, 19, 553-564.
[http://dx.doi.org/10.1109/TNANO.2020.3006114]
[21]
Mladenov, V. A new simplified model for HfO 2-based memristor. 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST), 13-15 May 2019 Thessaloniki, Greece 2019.
[22]
Rajendran, B.; Alibart, F. Neuromorphic computing based on emerging memory technologies. IEEE J. Emerg. Sel. Top. Circuits Syst., 2016, 6(2), 198-211.
[http://dx.doi.org/10.1109/JETCAS.2016.2533298]
[23]
Bunnam, T.; Soltan, A.; Sokolov, D.; Maevsky, O.; Degenaar, P.; Yakovlev, A. Empirical temperature model of self-directed channel memristor.2020 IEEE SENSORS; 25-28 October 2020 Rotterdam, Netherlands, 2020.
[24]
Pedretti, G.; Bianchi, S.; Milo, V.; Calderoni, A.; Ramaswamy, N.; Ielmini, D. Modeling-based design of brain-inspired spiking neural networks with RRAM learning synapses. 2017 IEEE International Electron Devices Meeting (IEDM), 02-06 December 2017 San Francisco, CA, USA 2017.
[http://dx.doi.org/10.1109/IEDM.2017.8268467]
[25]
Yu, S.; Wu, Y.; Jeyasingh, R.; Kuzum, D.; Wong, H.S.P. An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation. IEEE Trans. Electron Dev., 2011, 58(8), 2729-2737.
[http://dx.doi.org/10.1109/TED.2011.2147791]
[26]
Wang, J.J.; Hu, S.G.; Zhan, X.T.; Luo, Q.; Yu, Q.; Liu, Z.; Chen, T.P.; Yin, Y.; Hosaka, S.; Liu, Y. Predicting house price with a memristor-based artificial neural network. IEEE Access, 2018, 6, 16523-16528.
[http://dx.doi.org/10.1109/ACCESS.2018.2814065]
[27]
Park, J.; Kwon, M.W.; Kim, H.; Hwang, S.; Lee, J.J.; Park, B.G. Compact neuromorphic system with four-terminal Si-based synaptic devices for spiking neural networks. IEEE Trans. Electron Dev., 2017, 64(5), 2438-2444.
[http://dx.doi.org/10.1109/TED.2017.2685519]
[28]
Plank, J.S.; Schuman, C.D.; Bruer, G.; Dean, M.E.; Rose, G.S. The TENNLab exploratory neuromorphic computing framework. IEEE Lett. Comput. Soc., 2018, 1(2), 17-20.
[http://dx.doi.org/10.1109/LOCS.2018.2885976]
[29]
Jain, A.K.; Jianchang, M.; Mohiuddin, K.M. Artificial neural networks: A tutorial. Computer, 1996, 29(3), 31-44.
[http://dx.doi.org/10.1109/2.485891]
[30]
Sanca, G.A.; Di Francesco, F.; Caroli, N.; Garcia-Inza, M.; Golmar, F. Design of a simple readout circuit for resistive switching memristors based on CMOS inverters. 2018 IEEE 4th International Forum on Research and Technology for Society and Industry (RTSI), 10-13 September 2018 Palermo, Italy 2018.
[http://dx.doi.org/10.1109/RTSI.2018.8548456]
[31]
Prodromakis, T.; Michelakis, K.; Toumazou, C. Switching mechanisms in microscale memristors. Electron. Lett., 2010, 46(1), 63.
[http://dx.doi.org/10.1049/el.2010.2716]
[32]
Koo, M.; Srinivasan, G.; Shim, Y.; Roy, K. SBSNN: Stochastic-bits enabled binary spiking neural network with on-chip learning for energy efficient neuromorphic computing at the edge. IEEE Trans. Circuits Syst. I Regul. Pap., 2020, 67(8), 2546-2555.
[http://dx.doi.org/10.1109/TCSI.2020.2979826]
[33]
An, H.; Zhou, Z.; Yi, Y. Opportunities and challenges on nanoscale 3D neuromorphic computing system. 2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), 07-11 August 2017Washington, DC, USA 2017.
[http://dx.doi.org/10.1109/ISEMC.2017.8077906]
[34]
Kuzum, D.; Jeyasingh, R.G.D.; Yu, S.; Wong, H.S.P. Low-energy robust neuromorphic computation using synaptic devices. IEEE Trans. Electron Dev., 2012, 59(12), 3489-3494.
[http://dx.doi.org/10.1109/TED.2012.2217146]
[35]
Hamdioui, S.; Kvatinsky, S.; Cauwenberghs, G.; Xie, L.; Wald, N.; Joshi, S.; Elsayed, H.M.; Corporaal, H.; Bertels, K. Memristor for computing: Myth or reality?Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017; , 2017.
[http://dx.doi.org/10.23919/DATE.2017.7927083]
[36]
Panda, D.; Dhar, A.; Ray, S.K. Nonvolatile memristive switching characteristics of tio$_2$ films embedded with nickel nanocrystals. IEEE Trans. Nanotechnol., 2012, 11(1), 51-55.
[http://dx.doi.org/10.1109/TNANO.2011.2132142]
[37]
Chua, L. Resistance switching memories are memristors. In: Handbook of memristor networks; , 2019.
[38]
Ghedira, S.; Rziga, F.O.; Mbarek, K.; Besbes, K. Dynamical resistive switching of a generic memristor model: Analysis and simulation. 2017 International Conference on Engineering & MIS (ICEMIS), 08-10 May 2017, Monastir, Tunisia 2017.
[39]
Biolek, Z.; Biolek, D.; Biolková, V. Computation of the area of memristor pinched hysteresis loop. IEEE Trans. Circuits Syst. II Express Briefs, 2012, 59(9), 607-611.
[http://dx.doi.org/10.1109/TCSII.2012.2208670]
[40]
Yan, X.; Zhao, J.; Liu, S.; Zhou, Z.; Liu, Q.; Chen, J.; Liu, X.Y. Memristor with Ag‐cluster‐doped TiO2 films as artificial synapse for neuroinspired computing. Adv. Funct. Mater., 2018, 28(1), 1705320.
[http://dx.doi.org/10.1002/adfm.201705320]
[41]
Goi, E.; Zhang, Q.; Chen, X.; Luan, H.; Gu, M. Perspective on photonic memristive neuromorphic computing. PhotoniX, 2020, 1(1), 3.
[http://dx.doi.org/10.1186/s43074-020-0001-6]
[42]
Arnold, M.G.; Sample, N.J.; Shuler, J.D. Guidelines for safe simulation and synthesis of implicit style Verilog. Proceedings International Verilog HDL Conference and VHDL International Users Forum, 16-19 March 1998Santa Clara, CA, USA 1998.
[http://dx.doi.org/10.1109/IVC.1998.660681]
[43]
Xia, L.; Li, B.; Tang, T.; Gu, P.; Chen, P.Y.; Yu, S.; Cao, Y.; Wang, Y.; Xie, Y.; Yang, H. MNSIM: Simulation platform for memristor-based neuromorphic computing system. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., 2017, 37(5), 1.
[http://dx.doi.org/10.1109/TCAD.2017.2729466]
[44]
Kim, H.; Sah, M.P.; Yang, C.; Cho, S.; Chua, L.O. Memristor emulator for memristor circuit applications. IEEE Trans. Circuits Syst. I Regul. Pap., 2012, 59(10)
[45]
Andrews, R.J. The brain-machine interface: Nanotechnology and cybernetics 60 years after norbert wiener. In 2021 IEEE Conference on Norbert Wiener in the 21st Century (21CW), 22-25 July 2021 Chennai, India 2021.
[46]
Harris, W.A. Zero to Birth: How the Human Brain Is Built; Princeton University Press, 2022.
[47]
Tao, D-W.; Chen, J-B.; Jiang, Z-j.; Qi, B-J.; Zhang, K.; Wang, C-W. Making reversible transformation from electronic to ionic resistive switching possible by applied electric field in an asymmetrical Al/TiO2/FTO nanostructure. Appl. Surf. Sci., 2019.
[48]
Dongale, T.D.; Sutar, S.S.; Dange, Y.D.; Khot, A.C.; Kundale, S.S.; Patil, S.R.; Patil, S.V.; Patil, A.A.; Khot, S.S.; Patil, P.J.; Bae, J.; Kamat, R.K.; Kim, T.G. Machine learning-assisted design guidelines and performance prediction of CMOS-compatible metal oxide-based resistive switching memory devices. Appl. Mater. Today, 2022, 29, 101650.
[http://dx.doi.org/10.1016/j.apmt.2022.101650]
[49]
Dash, C.S.; Sahoo, S.; Prabaharan, S.R.S. Resistive switching and impedance characteristics of M/TiO2−x/TiO2/M nano-ionic memristor. Solid State Ion., 2018, 324, 218-225.
[http://dx.doi.org/10.1016/j.ssi.2018.07.012]
[50]
Muthulakshmi, S.; Dash, C.S.; Prabaharan, S.R.S. Memristor augmented approximate adders and subtractors for image processing applications: An approach. AEU Int. J. Electron. Commun., 2018, 91, 91-102.
[http://dx.doi.org/10.1016/j.aeue.2018.05.003]
[51]
Lu, A.; Peng, X.; Li, W.; Jiang, H.; Yu, S. NeuroSim validation with 40nm RRAM compute-in-memory macro. 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, 06-09 June 2021 Washington DC, DC, USA 2021.
[52]
Chen, J.; Wu, Y.; Zhu, K.; Sun, F.; Guo, C.; Wu, X.; Cheng, G.; Zheng, R. Core-shell copper nanowire-TiO2 nanotube arrays with excellent bipolar resistive switching properties. Electrochim. Acta, 2019, 316, 133-142.
[http://dx.doi.org/10.1016/j.electacta.2019.05.110]
[53]
Jeong, W.H.; Han, J.H.; Choi, B.J. Effect of Ag concentration dispersed in HfOx thin films on threshold switching. Nanoscale Res. Lett., 2020, 15(1), 27.
[http://dx.doi.org/10.1186/s11671-020-3258-6] [PMID: 32002695]
[54]
Wainstein, N.; Kvatinsky, S. TIME—Tunable inductors using memristors. IEEE Trans. Circuits Syst. I Regul. Pap., 2018, 65(5), 1505-1515.
[http://dx.doi.org/10.1109/TCSI.2017.2760625]
[55]
Adhikari, S.P.; Sah, M.P.; Kim, H.; Chua, L.O. Three fingerprints of memristor. IEEE Trans. Circuits Syst. I Regul. Pap., 2013, 60(11), 3008-3021.
[http://dx.doi.org/10.1109/TCSI.2013.2256171]
[56]
Li, D.; Ilyas, N.; Li, C.; Jiang, X.; Jiang, Y.; Li, W. Synaptic learning and memory functions in SiO 2:Ag/TiO 2 based memristor devices. J. Phys. D Appl. Phys., 2020, 53(17), 175102.
[http://dx.doi.org/10.1088/1361-6463/ab70c9]
[57]
Chakrabarti, S.; Panja, R.; Roy, S.; Roy, A.; Samanta, S.; Dutta, M.; Ginnaram, S.; Maikap, S.; Cheng, H.M.; Tsai, L.N.; Chang, Y.L. Evolution of resistive switching mechanism through H2O2 sensing by using TaOx-based material in W/Al2O3/TaOx/TiN structure. Appl. Surf. Sci., 2018, 433(1), 51-59.
[58]
Sokolov, A.S.; Jeon, Y.R.; Kim, S.; Ku, B.; Lim, D.; Han, H.; Chae, M.G.; Lee, J.; Ha, B.G.; Choi, C. Influence of oxygen vacancies in ALD HfO2-x thin films on non-volatile resistive switching phenomena with a Ti/HfO2-x/Pt structure. Appl. Surf. Sci., 2018, 434, 822-830.
[http://dx.doi.org/10.1016/j.apsusc.2017.11.016]
[59]
Kvatinsky, S.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. TEAM: Threshold adaptive memristor model. IEEE Trans. Circuits Syst. I Regul. Pap., 2013, 60(1), 211-221.
[http://dx.doi.org/10.1109/TCSI.2012.2215714]
[60]
Kvatinsky, S.; Ramadan, M.; Friedman, E.G.; Kolodny, A. VTEAM: A general model for voltage-controlled memristors. IEEE Trans. Circuits Syst. II Express Briefs, 2015, 62(8), 786-790.
[http://dx.doi.org/10.1109/TCSII.2015.2433536]
[61]
Hu, M.; Li, H.; Wu, Q.; Rose, G.S. Hardware realization of BSB recalls function using memristor crossbar arrays. DAC Design Automation Conference, 2012, p. 2012.
[http://dx.doi.org/10.1145/2228360.2228448]
[62]
Hu, M.; Li, H.; Chen, Y.; Wu, Q.; Rose, G.S.; Linderman, R.W. Memristor crossbar-based neuromorphic computing system: A case study. IEEE Trans. Neural Netw. Learn. Syst., 2014, 25(10), 1864-1878.
[http://dx.doi.org/10.1109/TNNLS.2013.2296777] [PMID: 25291739]
[63]
Qureshi, M.S.; Pickett, M.; Miao, F.; Strachan, J.P. CMOS interface circuits for reading and writing memristor crossbar array. 2011.IEEE International Symposium of Circuits and Systems (ISCAS), 15-18 May 2011Rio de Janeiro, Brazil 2011
[http://dx.doi.org/10.1109/ISCAS.2011.5938211]
[64]
Cassuto, Y.; Kvatinsky, S.; Yaakobi, E. Information-theoretic sneak-path mitigation in memristor crossbar arrays. IEEE Trans. Inf. Theory, 2016, 62(9), 4801-4813.
[http://dx.doi.org/10.1109/TIT.2016.2594798]
[65]
Chabi, D.; Zhao, W.; Querlioz, D.; Klein, J.O. Robust neural logic block (NLB) based on memristor crossbar array. 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 08-09 June 2011San Diego, CA, USA 2011.
[http://dx.doi.org/10.1109/NANOARCH.2011.5941495]
[66]
Hu, M.; Li, H.; Wu, Q.; Rose, G.S.; Chen, Y. Memristor crossbar-based hardware realization of BSB recall function. The 2012 International Joint Conference on Neural Networks (IJCNN), 10-15 June 2012 Brisbane, QLD, Australia 2012.
[http://dx.doi.org/10.1109/IJCNN.2012.6252563]
[67]
Yakopcic, C.; Taha, T.M. Energy efficient perceptron pattern recognition using segmented memristor crossbar arrays. International Joint Conference on Neural Networks (IJCNN), 04-09 August 2013Dallas, TX, USA 2013.
[http://dx.doi.org/10.1109/IJCNN.2013.6707073]
[68]
Thomas, S.A.; Vohra, S.K.; Kumar, R.; Sharma, R.; Das, D.M. Analysis of parasitics on CMOS based memristor crossbar array for neuromorphic systems. 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 09-11 August 2021Lansing, MI, USA2021.
[69]
Chua, L. Memristor: Remembrance of things past. IEEE Micro, 2018, 38(5), 7-12.
[http://dx.doi.org/10.1109/MM.2018.053631136]
[70]
Raja, T.; Mourad, S. Digital logic implementation in memristor-based crossbars-a tutorial. 2010.Fifth IEEE International Symposium on Electronic Design, Test & Applications, 13-15 January 2010Ho Chi Minh City, Vietnam 2010
[http://dx.doi.org/10.1109/DELTA.2010.70]
[71]
Liu, X.; Mao, M.; Liu, B.; Li, B.; Wang, Y.; Jiang, H.; Barnell, M.; Wu, Q.; Yang, J.; Li, H.; Chen, Y. Harmonica: A framework of heterogeneous computing systems with memristor-based neuromorphic computing accelerators. IEEE Trans. Circuits Syst. I Regul. Pap., 2016, 63(5), 617-628.
[http://dx.doi.org/10.1109/TCSI.2016.2529279]
[72]
Fiala, J.C. Three-dimensional structure of synapses in the brain and on the web. International Joint Conference on Neural Networks. IJCNN’02 (Cat. No. 02CH37290), 12-17 May 2002 Honolulu, HI, USA2002.
[http://dx.doi.org/10.1109/IJCNN.2002.1005432]
[73]
Danial, L.; Wainstein, N.; Kraus, S.; Kvatinsky, S. Breaking through the speed-power-accuracy tradeoff in ADCs using a memristive neuromorphic architecture. IEEE Trans. Emerg. Top. Comput. Intell., 2018, 2(5), 396-409.
[http://dx.doi.org/10.1109/TETCI.2018.2849109]
[74]
Rajendran, B.; Liu, Y.; Seo, J.; Gopalakrishnan, K.; Chang, L.; Friedman, D.J.; Ritter, M.B. Specifications of nanoscale devices and circuits for neuromorphic computational systems. IEEE Trans. Electron Dev., 2013, 60(1), 246-253.
[http://dx.doi.org/10.1109/TED.2012.2227969]
[75]
Pyo, Y.; Nahm, S.; Jeong, J. Classification performances due to asymmetric nonlinear weight updates in analog artificial synapse-based hardware neural networks. 10th International Winter Conference on Brain-Computer Interface (BCI), 21-23 February 2022Gangwon-do, Korea 2022.
[http://dx.doi.org/10.1109/BCI53720.2022.9734968]
[76]
Chebli, R.; Sawan, M. Low noise and high CMRR front-end amplifier dedicated to portable EEG acquisition system. 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 03-07 July 2013 Osaka, Japan2013.
[http://dx.doi.org/10.1109/EMBC.2013.6610053]
[77]
Pal, S.; Bose, S.; Ki, W.H.; Islam, A. Design of power-and variability-aware nonvolatile RRAM cell using memristor as a memory element. IEEE J. Electron Devices Soc., 2019, 7, 701-709.
[http://dx.doi.org/10.1109/JEDS.2019.2928830]
[78]
Al-Shedivat, M.; Naous, R.; Cauwenberghs, G.; Salama, K.N. Memristors empower spiking neurons with stochasticity. IEEE J. Emerg. Sel. Top. Circuits Syst., 2015, 5(2), 242-253.
[http://dx.doi.org/10.1109/JETCAS.2015.2435512]
[79]
Schemmel, J.; Grubl, A.; Meier, K.; Mueller, E. Implementing synaptic plasticity in a VLSI spiking neural network model. Ieee International Joint Conference On Neural Network Proceedings, 16-21 July 2006Vancouver, BC, Canada2006.
[80]
Mannan, Z.I.; Adhikari, S.P.; Yang, C.; Budhathoki, R.K.; Kim, H.; Chua, L. Memristive imitation of synaptic transmission and plasticity. IEEE Trans. Neural Netw. Learn. Syst., 2019, 30(11), 3458-3470.
[http://dx.doi.org/10.1109/TNNLS.2019.2892385] [PMID: 30762570]
[81]
Wijesinghe, P.; Ankit, A.; Sengupta, A.; Roy, K. An all-memristor deep spiking neural computing system: A step toward realizing the low-power stochastic brain. IEEE Trans. Emerg. Top. Comput. Intell., 2018, 2(5), 345-358.
[http://dx.doi.org/10.1109/TETCI.2018.2829924]
[82]
Turng, A. The chemical basis of morphogenesis. Philos. Trans. R. Soc. Lond. B Biol. Sci., 1952, 237.
[83]
Danial, L.; Gupta, V.; Pikhay, E.; Roizin, Y.; Kvatinsky, S. Modeling a floating-gatememristive device for computer aided design of neuromorphic computing.In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE); 09-13 March 2020 Grenoble, France, 2020.
[84]
Katumba, A.; Freiberger, M.; Laporte, F.; Lugnan, A.; Sackesyn, S.; Ma, C.; Dambre, J.; Bienstman, P. Neuromorphic computing based on silicon photonics and reservoir computing. IEEE J. Sel. Top. Quantum Electron., 2018, 24(6), 1-10.
[http://dx.doi.org/10.1109/JSTQE.2018.2821843]
[85]
Shi, L.; Pei, J.; Deng, N.; Wang, D.; Deng, L.; Wang, Y.; Zhang, Y.; Chen, F.; Zhao, M.; Song, S.; Zeng, F. Development of a neuromorphic computing system.IEEE international electron devices meeting (IEDM); 07-09 December 2015 Washington, DC, USA, 2015.
[86]
Sharma, A.A.; Bain, J.A.; Weldon, J.A. Phase coupling and control of oxide-based oscillators for neuromorphic computing. IEEE J. Explor. Solid-State Comput. Devices Circuits, 2015, 1, 58-66.
[http://dx.doi.org/10.1109/JXCDC.2015.2448417]
[87]
Chen, W.H.; Khwa, W.S.; Li, J.Y.; Lin, W.Y.; Lin, H.T.; Liu, Y.; Wang, Y.; Wu, H.; Yang, H.; Chang, M.F. Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing. 2017 18th International Symposium on Quality Electronic Design (ISQED), 14-15 March 2017 Santa Clara, CA, USA 2017.
[88]
Yakopcic, C.; Taha, T.M.; Subramanyam, G.; Pino, R.E.; Rogers, S. A memristor device model. IEEE Electron Device Lett., 2011, 32(10), 1436-1438.
[http://dx.doi.org/10.1109/LED.2011.2163292]
[89]
Wang, L.; Lei, B.; Li, Q.; Su, H.; Zhu, J.; Zhong, Y. Triple-memory networks: A brain-inspired method for continual learning. IEEE Trans. Neural Netw. Learn. Syst., 2022, 33(5), 1925-1934.
[http://dx.doi.org/10.1109/TNNLS.2021.3111019] [PMID: 34529579]
[90]
Shim, J. Selection of optimal reasoning path by bayesian switching mechanism in the brain sensory system. International Conference on Electronics, Information, and Communication (ICEIC), 22-25 January 2019Auckland, New Zealand 2019.
[http://dx.doi.org/10.23919/ELINFOCOM.2019.8706454]
[91]
Singh, J.K.; Kapur, G. A study of adaptive cmos circuits extracting feature of neuroplasticity in human brain. International Conference on Signal Processing and Communication (ICSC), 2019. 07-09 March 2019 NOIDA, India, pp. 349-354.
[http://dx.doi.org/10.1109/ICSC45622.2019.8938304]
[92]
Vogt, A.; Lauer, L.; Offenhausser, A. Controlled outgrowth and synapse formation of rat brain neurons by microcontact printing. Proceedings of the IEEE-EMBS Special Topic Conference on Molecular, Cellular and Tissue Engineering, 09-09 June 2002 Genoa, Italy 2002.
[http://dx.doi.org/10.1109/MCTE.2002.1175027]
[93]
Veletić M.; Balasingham, I. Synaptic communication engineering for future cognitive brain–machine interfaces. Proc. IEEE, 2019, 107(7), 1425-1441.
[http://dx.doi.org/10.1109/JPROC.2019.2915199]
[94]
Gi, S.; Yeo, I.; Chu, M.; Kim, S.; Lee, B. Fundamental issues of implementing hardware neural networks using memristor. 2015 International SoC Design Conference (ISOCC), 02-05 November 2015 Gyeongju, Korea (South) 2015.
[http://dx.doi.org/10.1109/ISOCC.2015.7401790]
[95]
Kheradpisheh, S.R.; Masquelier, T. Temporal backpropagation for spiking neural networks with one spike per neuron. Int. J. Neural Syst., 2020, 30(6), 2050027.
[http://dx.doi.org/10.1142/S0129065720500276] [PMID: 32466691]
[96]
Zhang, M.; Long, S.; Wang, G.; Li, Y.; Xu, X.; Liu, H.; Liu, R.; Wang, M.; Li, C.; Sun, P.; Sun, H.; Liu, Q.; Lü, H.; Liu, M. An overview of the switching parameter variation of RRAM. Chin. Sci. Bull., 2014, 59(36), 5324-5337.
[http://dx.doi.org/10.1007/s11434-014-0673-z]
[97]
Frascaroli, J. Harmonica: A framework of heterogeneous computing systems with memristor-based neuromorphic computing accelerators. IEEE TCAS-I, 2016, 63(5), 617-628.
[98]
Tan, Z.J. Multilayer thin film oxides for resistive switching; Doctoral dissertation, Massachusetts Institute of Technology, 2019.
[99]
Boahen, K.A. Point-to-point connectivity between neuromorphic chips using address events. IEEE Trans. Circuits Syst., 2 Analog. Digit. Signal Process., 2000, 47(5), 416-434.
[http://dx.doi.org/10.1109/82.842110]
[100]
Yao, P.; Wu, H.; Gao, B.; Tang, J.; Zhang, Q.; Zhang, W.; Yang, J.J.; Qian, H. Fully hardware-implemented memristor convolutional neural network. Nature, 2020, 577(7792), 641-646.
[http://dx.doi.org/10.1038/s41586-020-1942-4] [PMID: 31996818]
[101]
Liu, T.; Quan, G.; Wen, W. Fpt-spike: A flexible precise-time-dependent single-spike neuromorphic computing architecture. CCF THPC, 2020, 2(3), 254-271.
[102]
Staudigl, F.; Merchant, F.; Leupers, R. A survey of neuromorphic computing-in-memory: architectures, simulators, and security. IEEE Des. Test, 2022, 39(2), 90-99.
[http://dx.doi.org/10.1109/MDAT.2021.3102013]
[103]
Pastur-Romay, L.; Cedrón, F.; Pazos, A.; Porto-Pazos, A. Deep artificial neural networks and neuromorphic chips for big data analysis: pharmaceutical and bioinformatics applications. Int. J. Mol. Sci., 2016, 17(8), 1313.
[http://dx.doi.org/10.3390/ijms17081313] [PMID: 27529225]
[104]
Gouaux, E. Structure and function of AMPA receptors. J. Physiol., 2004, 554(2), 249-253.
[http://dx.doi.org/10.1113/jphysiol.2003.054320] [PMID: 14645452]
[105]
Alt, A.; Nisenbaum, E.S.; Bleakman, D.; Witkin, J.M. A role for AMPA receptors in mood disorders. Biochem. Pharmacol., 2006, 71(9), 1273-1288.
[http://dx.doi.org/10.1016/j.bcp.2005.12.022] [PMID: 16442080]
[106]
Malinow, R.; Malenka, R.C. AMPA receptor trafficking and synaptic plasticity. Annu. Rev. Neurosci., 2002, 25(1), 103-126.
[http://dx.doi.org/10.1146/annurev.neuro.25.112701.142758] [PMID: 12052905]
[107]
Samardzic, N.M.; Bajic, J.S.; Sekulic, D.L.; Dautovic, S. Volatile memristor in leaky integrate-and-fire neurons: Circuit simulation and experimental study. Electronics, 2022, 11(6), 894.
[http://dx.doi.org/10.3390/electronics11060894]
[108]
Lin, J.; Ye, W.; Zhang, X.; Lian, Q.; Wu, S.; Guo, T.; Chen, H. A memristor-based leaky integrate-and-fire artificial neuron with tunable performance. IEEE Electron Device Lett., 2022, 43(8), 1231-1234.
[http://dx.doi.org/10.1109/LED.2022.3184671]
[109]
Razi, M.; Athappilly, K. A comparative predictive analysis of neural networks (NNs), nonlinear regression and classification and regression tree (CART) models. Expert Syst. Appl., 2005, 29(1), 65-74.
[http://dx.doi.org/10.1016/j.eswa.2005.01.006]
[110]
Buscarino, A.; Corradino, C.; Fortuna, L.; Frasca, M.; Chua, L.O. Turing patterns in memristive cellular nonlinear networks. IEEE Trans. Circuits Syst. I Regul. Pap., 2016, 63(8), 1222-1230.
[http://dx.doi.org/10.1109/TCSI.2016.2564738]
[111]
Buscarino, A.; Fortuna, L.; Frasca, M.; Gambuzza, L.V.; Sciuto, G. Memristive chaotic circuits based on cellular nonlinear networks. Int. J. Bifurcat. Chaos, 2012, 22(3), 1250070.
[http://dx.doi.org/10.1142/S0218127412500708]
[112]
Gambuzza, L.V.; Buscarino, A.; Fortuna, L.; Frasca, M. Memristor-based adaptive coupling for consensus and synchronization. IEEE Trans. Circuits Syst. I Regul. Pap., 2015, 62(4), 1175-1184.
[http://dx.doi.org/10.1109/TCSI.2015.2395631]
[113]
Buscarino, A.; Corradino, C.; Fortuna, L.; Frasca, M.; Chua, L.O. Evidence of turing patterns in memristive cellular nonlinear networks. 15th International Workshop on Cellular Nanoscale Networks and their Applications, 23-25 August 2016Dresden, Germany 2016.
[114]
Buscarino, A.; Corradino, C.; Fortuna, L.; Frasca, M. Turing patterns via pinning control in the simplest memristive cellular nonlinear networks. Chaos, 2019, 29(10), 103145.
[http://dx.doi.org/10.1063/1.5115131] [PMID: 31675834]
[115]
Zhu, L.; He, L. Two different approaches for parameter identification in a spatial–temporal rumor propagation model based on Turing patterns. Commun. Nonlinear Sci. Numer. Simul., 2022, 107, 106174.
[http://dx.doi.org/10.1016/j.cnsns.2021.106174]
[116]
Bucolo, M.; Buscarino, A.; Corradino, C.; Fortuna, L.; Frasca, M. Turing patterns in the simplest MCNN. NOLTA, 2019, 10(4), 390-398.

Rights & Permissions Print Cite
© 2024 Bentham Science Publishers | Privacy Policy