Login Register Cart 0
Generic placeholder image

Current Nanoscience

Editor-in-Chief

ISSN (Print): 1573-4137
ISSN (Online): 1875-6786

Back
Journal Home About Journal Editorial Board Journal Insight Current Issue Volumes/Issues
Subscribe
Review Article

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Author(s): Mehwish Maqbool and Vijay Kumar Sharma*

Volume 20, Issue 4, 2024

Published on: 09 June, 2023

Page: [459 - 470] Pages: 12

DOI: 10.2174/1573413719666230510101913

Price: $65

conference banner
Abstract

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems.

Objectives: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems.

Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region.

Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters.

Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

« Previous Next »
Graphical Abstract

[1]
Sharma, V.K.; Pattanaik, M. A reliable ground bounce noise reduction technique for nanoscale CMOS circuits. Int. J. Electron., 2015, 102(11), 1852-1866.
[http://dx.doi.org/10.1080/00207217.2014.996786]
[2]
Mushtaq, U.; Sharma, V.K. Design and analysis of INDEP FinFET SRAM cell at 7‐nm technology. Int. J. Numer. Model., 2020, 33(5), e2730.
[http://dx.doi.org/10.1002/jnm.2730]
[3]
Sharma, V.K. A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime. Aust. Electric. Electr. Eng., 2021, 18(4), 217-236.
[http://dx.doi.org/10.1080/1448837X.2021.1966957]
[4]
Atalla, M.M.; Tannenbaum, E.; Scheibner, E.J. Stabilization of silicon surfaces by thermally grown oxides. Bell Syst. Tech. J., 1959, 38(3), 749-783.
[http://dx.doi.org/10.1002/j.1538-7305.1959.tb03907.x]
[5]
Cheng, Y.; Hu, C. MOSFET modeling & BSIM3 user’s guide; Springer Science & Business Media: Berlin, Germany, 1999.
[6]
Gupta, K.M.; Gupta, N.; Gupta, K.M.; Gupta, N. Metal semiconductor field effect transistors, MOS transistors, and charge coupled device. Adv. Semicond. Mater. Dev., 2016, 2016, 385-414.
[http://dx.doi.org/10.1007/978-3-319-19758-6_11]
[7]
Sharma, V.K.; Pattanaik, M. Design of low leakage variability aware ONOFIC CMOS standard cell library. J. Circuits Syst. Comput., 2016, 25(11), 1650134.
[http://dx.doi.org/10.1142/S0218126616501346]
[8]
Sharma, V.K.; Patel, S.; Pattanaik, M. High performance process variations aware technique for sub-threshold 8T-SRAM cell. Wirel. Pers. Commun., 2014, 78(1), 57-68.
[http://dx.doi.org/10.1007/s11277-014-1735-x]
[9]
Ytterdal, T.; Cheng, Y.; Fjeldly, T.A. MOSFET device physics and operation. In: Device Modeling for Analog and RF CMOS Circuit Design; John Wiley and Sons: Hobokeu, New Jersey, 2003; 2003, pp. 1-45.
[10]
Sharma, V.K.; Soni, S. Comparison among different CMOS inverter for low leakage at different technologies. Int. J. Appl. Eng. Res., 2010, 1(2), 228.
[11]
Sharma, V.K. Optimal design for 1:2n demultiplexer using QCA nanotechnology with energy dissipation analysis. Int. J. Numer. Model., 2021, 34(6), e2907.
[http://dx.doi.org/10.1002/jnm.2907]
[12]
Ezzat, M.A.; Ezzat, S.M.; Alduraibi, N.S. On size-dependent thermo-viscoelasticity theory for piezoelectric materials. Waves Random Complex Media, 2022, 2022, 1-23.
[http://dx.doi.org/10.1080/17455030.2022.2043569]
[13]
Mushtaq, U.; Sharma, V.K. Performance analysis for reliable nanoscaled FinFET logic circuits. Analog Integr. Circuits Signal Process., 2021, 107(3), 671-682.
[http://dx.doi.org/10.1007/s10470-020-01765-z]
[14]
Kajal; Sharma, V.K. A novel low power technique for FinFET domino OR logic. J. Circuits Syst. Comput., 2021, 30(7), 2150117.
[http://dx.doi.org/10.1142/S0218126621501176]
[15]
Kajal; Sharma, V.K. Design and Simulation for NBTI Aware Logic Gates. Wirel. Pers. Commun., 2021, 120(2), 1525-1542.
[http://dx.doi.org/10.1007/s11277-021-08522-z]
[16]
Riyaz, S.; Naz, S.F.; Sharma, V.K. Multioperative reversible gate design with implementation of 1‐bit full adder and subtractor along with energy dissipation analysis. Int. J. Circuit Theory Appl., 2021, 49(4), 990-1012.
[http://dx.doi.org/10.1002/cta.2886]
[17]
Riyaz, S.; Sharma, V.K. Design of reversible Feynman and double Feynman gates in quantum-dot cellular automata nanotechnology. Circuit World, 2021, 49(1), 28-37.
[http://dx.doi.org/10.1108/CW-08-2020-0199]
[18]
Ahangaran, M.; Taghizadeh, N.; Beigy, H. Associative cellular learning automata and its applications. Appl. Soft Comput., 2017, 53, 1-18.
[http://dx.doi.org/10.1016/j.asoc.2016.12.006]
[19]
Raina, B.; Verma, C.; Gupta, M.; Sharma, V.K. Binary coded decimal (BCD) seven segment circuit designing using quantum-dot cellular automata (QCA). In 2021 5th International Conference on Trends in Electronics and Informatics (ICOEI), 03-05 June, 2021, Tirunelveli, India2021, p. 126-130.
[http://dx.doi.org/10.1109/ICOEI51242.2021.9453046]
[20]
Ganesh, E.N. Implementation and simulation of arithmetic logic unit, shifter and multiplier in Quantum cellular automata technology. Int. J. Comput. Sci. Eng., 1824, 2(5), 2010.
[21]
Cui, Y.; Zhong, Z.; Wang, D.; Wang, W.U.; Lieber, C.M. High performance silicon nanowire. Nano, 2003, 3(1), 149-152.
[http://dx.doi.org/10.1021/nl025875l]
[22]
Zhang, A.; Zheng, G.; Lieber, C.M. Nanowire field-effect transistor sensors; Nanowires, 2016, pp. 255-275.
[http://dx.doi.org/10.1007/978-3-319-41981-7_10]
[23]
Yan, Q.; Huang, B.; Yu, J.; Zheng, F.; Zang, J.; Wu, J.; Gu, B.L.; Liu, F.; Duan, W. Intrinsic current-voltage characteristics of graphene nanoribbon transistors and effect of edge doping. Nano Lett., 2007, 7(6), 1469-1473.
[http://dx.doi.org/10.1021/nl070133j] [PMID: 17461605]
[24]
Wessely, PJ; Wessely, F; Birinci, E; Schwalke, U; Riedinger, B Transfer-free fabrication of graphene transistors. J. Vac. Sci. Technol. B, Nanotechnol. Microelectron. Mater. Process. Meas. Phenom., 2012, 30(3), 03D114.
[25]
Fiori, G.; Iannaccone, G. Simulation of graphene nanoribbon field-effect transistors. IEEE Electron Device Lett., 2007, 28(8), 760-762.
[http://dx.doi.org/10.1109/LED.2007.901680]
[26]
Ezzat, M.A.; Ezzat, S.M.; Alkharraz, M.Y. State-space approach to nonlocal thermo-viscoelastic piezoelectric materials with fractional dual-phase lag heat transfer. Int. J. Numer. Methods Heat Fluid Flow, 2022, 32(12), 3726-3750.
[http://dx.doi.org/10.1108/HFF-02-2022-0097]
[27]
Pachori, A.; Suhane, P. Design and modelling of standalone hybrid power. 28th AHR Symp Hydraul Mach Syst Grenoble, 2016, 1(2), pp. 65-71.
[28]
Sharma, V.K. CNTFET circuit-based wide fan-in domino logic for low power applications. J. Circuits Syst. Comput., 2022, 31(2), 2250036.
[http://dx.doi.org/10.1142/S0218126622500360]
[29]
Bikshalu, K.; Reddy, V.S.K.; Reddy, P.C.S.; Rao, K.V. High-performance carbon nanotube field effect transistors with high k dielectric gate material. Mater. Today Proc., 2015, 2(9), 4457-4462.
[http://dx.doi.org/10.1016/j.matpr.2015.10.048]
[30]
Popov, V. Carbon nanotubes: properties and application. Mater. Sci. Eng. Rep., 2004, 43(3), 61-102.
[http://dx.doi.org/10.1016/j.mser.2003.10.001]
[31]
Ghasempour, R.; Narei, H. CNT basics and characteristics. In: Carbon nanotube-reinforced polymers; Elsevier: Amsterdam, 2018.
[http://dx.doi.org/10.1016/B978-0-323-48221-9.00001-7]
[32]
Li, H.; Yin, W.Y.; Banerjee, K.; Mao, J.F. Circuit modeling and performance analysis of multi-walled carbon nanotube interconnects. IEEE Trans. Electron Dev., 2008, 55(6), 1328-1337.
[http://dx.doi.org/10.1109/TED.2008.922855]
[33]
Merkoçi, A. Carbon nanotubes in analytical sciences. Microchim Acta., 2006, 152(3-4 SPEC.), 157-74.
[http://dx.doi.org/10.1007/s00604-005-0439-z]
[34]
Kim, J.; Page, A.J.; Irle, S.; Morokuma, K. Dynamics of local chirality during SWCNT growth: armchair versus zigzag nanotubes. J. Am. Chem. Soc., 2012, 134(22), 9311-9319.
[http://dx.doi.org/10.1021/ja301299t] [PMID: 22571240]
[35]
Chowdhry, A.; Kaur, J.; Khatri, M.; Puri, V.; Tuli, R.; Puri, S. Characterization of functionalized multiwalled carbon nanotubes and comparison of their cellular toxicity between HEK 293 cells and zebra fish in vivo. Heliyon, 2019, 5(10), e02605.
[http://dx.doi.org/10.1016/j.heliyon.2019.e02605] [PMID: 31687491]
[36]
Abdallah, B.; Elhissi, A.M.A.; Ahmed, W. Carbon nanotubes drug delivery. In: Advances in Medical and Surgical Engineering; Elsevier Inc.: Amsterdam, 2020; pp. 313-332.
[37]
Tambraparni, M.; Wang, S. Separation of metallic and semiconducting carbon nanotubes. Recent Pat. Nanotechnol., 2010, 4(1), 1-9.
[http://dx.doi.org/10.2174/187221010790712084] [PMID: 20180755]
[38]
Boumia, L; Zidour, M; Benzair, A; Tounsi, A. A Timoshenko beam model for vibration analysis of chiral single-walled carbon nanotubes. Phys E Low-Dimensional Syst Nanostructures., 2014, 59(5), 186-91.
[http://dx.doi.org/10.1016/j.physe.2014.01.020]
[39]
Pandey, P.; Dahiya, M. Carbon nanotubes: Types, methods of preparation and applications. Int. J. Pharm. Sci. Res., 2016, (6), 15-21.
[40]
Zahoor, F.; Hussin, F.A.; Khanday, F.A.; Ahmad, M.R.; Mohd Nawi, I.; Ooi, C.Y.; Rokhani, F.Z. Carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) based ternary combinational logic circuits. Electronics, 2021, 10(1), 79.
[http://dx.doi.org/10.3390/electronics10010079]
[41]
Khan, I.A.; Alam, N. CNTFET based circuit design for improved performance. Proc - 2019 Int Conf Electr Electron Comput Eng UPCON 2019., 08-10 Nov, 2019, Aligarh, India 2019, p. 1-5.
[http://dx.doi.org/10.1109/UPCON47278.2019.8980053]
[42]
Keshavarzian, P.; Sarikhani, R. A novel CNTFET-based ternary full adder. Circuits Syst. Signal Process., 2014, 33(3), 665-679.
[http://dx.doi.org/10.1007/s00034-013-9672-6]
[43]
Dang, T.; Anghel, L.; Leveugle, R. CNTFET basics and simulation. International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. 05-07 Sept, 2006, Tunis, Tunisia, pp. 28-33.
[http://dx.doi.org/10.1109/DTIS.2006.1708731]
[44]
Kabir, M.A.; Nandy, T.; Aminul Haque, M.; Dutta, A.; Mahmood, Z.H. Performance analysis of cntfet and mosfet focusing channel length, carrier mobility and ballistic conduction in high speed switching. Int. J. Adv. Mater. Sci. Engin., 2014, 3(4), 1-11.
[http://dx.doi.org/10.14810/ijamse.2014.3401]
[45]
Yao, X.; Zhang, Y.; Jin, W.; Hu, Y.; Cui, Y. Carbon nanotube field-effect transistor-based chemical and biological sensors. Sensors, 2021, 21(3), 995.
[http://dx.doi.org/10.3390/s21030995] [PMID: 33540641]
[46]
Qin, L.C. Determination of the chiral indices (n,m) of carbon nanotubes by electron diffraction. Phys. Chem. Chem. Phys., 2007, 9(1), 31-48.
[http://dx.doi.org/10.1039/B614121H] [PMID: 17164886]
[47]
Sinha, S.K.; Choudhury, S. CNTFET based Logic Circuits  A Brief Review. Int. J. Emerg. Technol. Adv. Eng., 2012, 2(4), 500-504.
[48]
Moaiyeri, M.H.; Mirzaee, R.F.; Doostaregan, A.; Navi, K.; Hashemipour, O. A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits. IET Comput. Digit. Tech., 2013, 7(4), 167-181.
[http://dx.doi.org/10.1049/iet-cdt.2013.0023]
[49]
Kim, Y.B.; Kim, Y. Bin, Lombardi F. A novel design methodology to optimize the speed and power of the CNTFET circuits; Midwest Symp Circuits Syst, 2009, pp. 1130-1133.
[50]
Lin, S.; Kim, Y.B.; Lombardi, F. CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol., 2011, 10(2), 217-225.
[http://dx.doi.org/10.1109/TNANO.2009.2036845]
[51]
Zahoor, F.; Hussin, F.A.; Khanday, F.A.; Ahmad, M.R.; Nawi, I.M.; Gupta, S. Carbon nanotube field effect transistor and resistive random access memory based 2-bit ternary comparator.Int Conf Intell Adv Syst Enhanc Present a Sustain Futur ICIAS; 13-15 July, 2021. Kuching, Malaysia, 2021.
[52]
Deng, J.; Wong, H.S.P. A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - Part II: Full device model and circuit performance benchmarking. IEEE Trans. Electron Dev., 2007, 54(12), 3195-3205.
[http://dx.doi.org/10.1109/TED.2007.909043]
[53]
Prasad, V.; Das, D. A review on MOSFET-Like CNTFETs. Sci. Technol. J., 2016, 4(2), 124-129.
[http://dx.doi.org/10.22232/stj.2016.04.02.06]
[54]
Diabi, A.; Hocini, A. Compact modeling of the performance of SB-CNTFET as a function of geometrical and physical parameters. Acta Phys. Pol. A, 2015, 127(4), 1124-1127.
[http://dx.doi.org/10.12693/APhysPolA.127.1124]
[55]
Moaiyeri, M.H.; Mirzaee, R.F.; Navi, K.; Momeni, A. Design and analysis of a high-performance CNFET-based Full Adder. Int. J. Electron., 2012, 99(1), 113-130.
[http://dx.doi.org/10.1080/00207217.2011.623269]
[56]
Appenzeller, J.; Lin, Y.M.; Knoch, J.; Chen, Z.; Avouris, P. Comparing carbon nanotube transistors-the ideal choice: A novel tunneling device design. IEEE Trans. Electron Dev., 2005, 52(12), 2568-2576.
[http://dx.doi.org/10.1109/TED.2005.859654]
[57]
Tiwari, S. CNTFETs the next generation of FETs. Int J Eng Dev Res., 2014, 2(4), 3377-3389.
[58]
Chandrashekar, P.; Karthik, R.; Krishna, O.K.S.; Bhavana, A. Design of low threshold full adder cell using CNTFET. Int. J. Appl. Eng. Res., 2017, 12(12), 3411-3415.
[59]
Farhana, S.; Alam, A.H.M.Z.; Khan, S. Spice model design for carbon nanotube field effect transistor (CNTFET). IEEE Int Conf Semicond Electron Proceedings, ICSE, 23-25 Sept, 2014, Kuala Lumpur, Malaysia 2014, p. 197-200.
[60]
Ghasemi Nejad Raeini, A.; Kordrostami, Z. Asymmetric lightly doped Schottky barrier CNTFET. Micro & Nano Lett., 2016, 11(3), 169-173.
[http://dx.doi.org/10.1049/mnl.2015.0434]
[61]
Azimi, N.; Hoseini, H.; Shahsavari, A. Designing a Novel Ternary Multiplier Using CNTFET. Int. J. Modern Edu. Comput. Sci., 2014, 6(11), 45-51.
[http://dx.doi.org/10.5815/ijmecs.2014.11.06]
[62]
Tomar, M.K.; Singh, V.; Laxya, L. A study on development of CNTFET based analog and digital circuits. In 2021 4th International Conference on Recent Developments in Control, Automation & Power Engineering (RDCAPE), 07-08 October 2021, Noida, India 2021, p. 392-398.
[http://dx.doi.org/10.1109/RDCAPE52977.2021.9633592]
[63]
Hatefinasab, S. CNTFET-based design of a high-efficient full adder using XOR logic. J Nano- Electron Phys., 2016, 8(4), 6-11.
[64]
Sankar, P.A.G.; Udhayakumar, K. MOSFET-like CNFET based logic gate library for low-power application: a comparative study. J. Semicond., 2014, 35(7), 075001.
[http://dx.doi.org/10.1088/1674-4926/35/7/075001]
[65]
Sharifi, F.; Moaiyeri, M.H.; Navi, K.; Bagherzadeh, N. Quaternary full adder cells based on carbon nanotube FETs. J. Comput. Electron., 2015, 14(3), 762-772.
[http://dx.doi.org/10.1007/s10825-015-0714-0]
[66]
O’connor, I.; Liu, J.; Gaffiot, F. CNTFET-based logic circuit design. In International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., 05-07 Sept, 2006, Tunis, Tunisia 2006, pp. 46-51.
[67]
Che, Y.; Chen, H.; Gui, H.; Liu, J.; Liu, B.; Zhou, C. Review of carbon nanotube nanoelectronics and macroelectronics. Semicond. Sci. Technol., 2014, 29(7), 073001.
[http://dx.doi.org/10.1088/0268-1242/29/7/073001]
[68]
Phanindra, L.S.; Rajath, M.N.; Rakesh, V.; Vasundara, P.K.S. A novel design and implementation of multi-valued logic arithmetic full adder circuit using CNTFET. 2016 IEEE Int Conf Recent Trends Electron Inf Commun Technol RTEICT 2016 - Proc., 20-21 May2016. Bangalore, India, pp. 563-8.
[69]
Li, H.; Zou, J.; Zhang, Q. Carbon nanotube-gated carbon nanotube field-effect transistors. Nanosci. Nanotechnol. Lett., 2010, 2(1), 21-25.
[http://dx.doi.org/10.1166/nnl.2010.1053]
[70]
Sabry Aly, M.M.; Gao, M.; Hills, G.; Lee, C.S.; Pitner, G.; Shulaker, M.M.; Wu, T.F.; Asheghi, M.; Bokor, J.; Franchetti, F.; Goodson, K.E.; Kozyrakis, C.; Markov, I.; Olukotun, K.; Pileggi, L.; Pop, E.; Rabaey, J.; Re, C.; Wong, H-S.P.; Mitra, S. Energy-efficient abundant-data computing: The N3XT 1,000 x. Computer, 2015, 48(12), 24-33.
[http://dx.doi.org/10.1109/MC.2015.376]
[71]
Pandey, G.K.; Tripathi, U.N.; Mishra, M. Top gate planner carbon nanotube field effect transistor using nanohub. Int. J. Appl. Eng. Res., 2018, 13(7), 973-4562.
[72]
Yang, M.H.; Teo, K.B.K.; Gangloff, L.; Milne, W.I.; Hasko, D.G.; Robert, Y.; Legagneux, P. Advantages of top-gate, high-k dielectric carbon nanotube field-effect transistors. Appl. Phys. Lett., 2006, 88(11), 113507.
[http://dx.doi.org/10.1063/1.2186100]
[73]
Chen, Z.; Farmer, D.; Xu, S.; Gordon, R.; Avouris, P.; Appenzeller, J. Externally assembled gate-all-around carbon nanotube field-effect transistor. IEEE Electron Device Lett., 2008, 29(2), 183-185.
[http://dx.doi.org/10.1109/LED.2007.914069]
[74]
Franklin, A.D.; Koswatta, S.O.; Farmer, D.B.; Smith, J.T.; Gignac, L.; Breslin, C.M.; Han, S.J.; Tulevski, G.S.; Miyazoe, H.; Haensch, W.; Tersoff, J. Carbon nanotube complementary wrap-gate transistors. Nano Lett., 2013, 13(6), 2490-2495.
[http://dx.doi.org/10.1021/nl400544q] [PMID: 23638708]
[75]
Ganie, S.S.; Singh, A. Gate All around CNTFET based ternary content addressable memory. ECS J. Solid State Sci. Technol., 2022, 11(6), 061006.
[http://dx.doi.org/10.1149/2162-8777/ac77bc]
[76]
Moaiyeri, M.H.; Razi, F. Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance. J. Comput. Electron., 2017, 16(2), 240-252.
[http://dx.doi.org/10.1007/s10825-017-0980-0]
[77]
Tarakanov, Y.A.; Kinaret, J.M. A carbon nanotube field effect transistor with a suspended nanotube gate. Nano Lett., 2007, 7(8), 2291-2294.
[http://dx.doi.org/10.1021/nl070891+] [PMID: 17604404]
[78]
Jakubinek, M.B.; Johnson, M.B.; White, M.A.; Jayasinghe, C.; Li, G.; Cho, W.; Schulz, M.J.; Shanov, V. Thermal and electrical conductivity of array-spun multi-walled carbon nanotube yarns. Carbon, 2012, 50(1), 244-248.
[http://dx.doi.org/10.1016/j.carbon.2011.08.041]
[79]
Hurst, S.L. Multiple-valued logic-its status and its future. IEEE Trans. Comput., 1984, 33(12), 1160-1179.
[http://dx.doi.org/10.1109/TC.1984.1676392]
[80]
Allen, C.M.; Givone, D.D. A minimization technique for multiple-valued logic systems. IEEE Trans. Comput., 1968, 17(2), 182-184.
[http://dx.doi.org/10.1109/TC.1968.227407]
[81]
Smith, K.C. The prospects for multivalued logic: A technology and applications view. IEEE Trans. Comput., 1981, 30(9), 619-634.
[http://dx.doi.org/10.1109/TC.1981.1675860]
[82]
Dubrova, E. Multiple-valued logic in VLSI: Challenges and opportunities. Proc NORCHIP, 1999, pp. 340-50. Available from: https://people.kth.se/~dubrova/PAPERS/NORCHIP99b.pdf
[83]
Asibelagh, A.G.; Mirzaee, R.F. Applicability of partial ternary full adder in ternary arithmetic units. arXiv 1902.06742, 2019.
[84]
Balla, P.C.; Antoniou, A. Low power dissipation MOS ternary logic family. IEEE J. Solid-State Circuits, 1984, 19(5), 739-749.
[http://dx.doi.org/10.1109/JSSC.1984.1052216]
[85]
Srivastava, A.; Venkatapathy, K. Design and implementation of a low power ternary full adder. VLSI Des., 1996, 4(1), 75-81.
[http://dx.doi.org/10.1155/1996/94696]
[86]
Ebrahimi, S.A.; Saeid, P.K.; Sorouri, M. Low power CNTFET-based ternary full adder cell for nanoelectronics. Int. J. Soft Comput. Eng., 2012, 2(2), 291-295.
[87]
Murotiya, S.L.; Gupta, A.; Vasishth, S. CNTFET-based design of dynamic ternary full adder cell. 11th IEEE India Conf Emerg Trends Innov Technol INDICON 2014, 02-05 August 2009Cancun, Mexico 2015.
[88]
Tabrizchi, S.; Panahi, A.; Sharifi, F.; Navi, K.; Bagherzadeh, N. Method for designing ternary adder cells based on CNFETs. IET Circuits Dev. Syst., 2017, 11(5), 465-470.
[http://dx.doi.org/10.1049/iet-cds.2016.0443]
[89]
Ghanatghestani, M.M.; Ghavami, B.; Pedram, H. A ternary full adder cell based on carbon nanotube FET for high-speed arithmetic units. J. Nanoelectr. Optoelect., 2018, 13(3), 368-377.
[http://dx.doi.org/10.1166/jno.2018.2244]
[90]
Sharifi, F.; Panahi, A.; Moaiyeri, M.H.; Sharifi, H.; Navi, K. High performance CNFET-based ternary full adders. J. Inst. Electron. Telecommun. Eng., 2018, 64(1), 108-115.
[http://dx.doi.org/10.1080/03772063.2017.1338973]
[91]
Firouzi, S.; Tabrizchi, S.; Sharifi, F.; Badawy, A.H. High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design. Comput. Electr. Eng., 2019, 77, 205-216.
[http://dx.doi.org/10.1016/j.compeleceng.2019.05.018]
[92]
Salehabad, I.M.; Navi, K.; Hosseinzadeh, M. Two novel inverter-based ternary full adder cells using CNFETs for energy-efficient applications. Int. J. Electron., 2019, 1-17.
[93]
Mahboob Sardroudi, F.; Habibi, M.; Moaiyeri, M.H. A low-power dynamic ternary full adder using carbon nanotube field-effect transistors. AEU Int. J. Electron. Commun., 2021, 131(1), 153600.
[http://dx.doi.org/10.1016/j.aeue.2020.153600]
[94]
Tabrizchi, S.; Sharifi, F.; Dehghani, P. Energy-Efficient and PVT-Tolerant CNFET-based ternary full adder cell. Circuits Syst. Signal Process., 2021, 40(7), 3523-3535.
[http://dx.doi.org/10.1007/s00034-020-01638-w]
[95]
Hosseini, S.A.; Etezadi, S. A novel low-complexity and energy-efficient ternary full adder in nanoelectronics. Circuits Syst. Signal Process., 2021, 40(3), 1314-1332.
[http://dx.doi.org/10.1007/s00034-020-01519-2]
[96]
Vidhyadharan, A.S.; Vidhyadharan, S. Mux based ultra-low-power ternary adders and multiplier implemented with CNFET and 45 nm MOSFETs. Int. J. Electron., 2022, 109(1), 58-82.
[http://dx.doi.org/10.1080/00207217.2021.1908616]

Rights & Permissions Print Cite
© 2024 Bentham Science Publishers | Privacy Policy