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ISSN (Print): 2352-0965
ISSN (Online): 2352-0973

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Research Article

Design and Analysis of a Radiation Resistant 12T SRAM Cell for Aerospace Applications

Author(s): Pavankumar Bikki*, M.L.V.V. Bharathi and K. Madhavi Jyothi

Volume 16, Issue 4, 2023

Published on: 23 January, 2023

Page: [372 - 379] Pages: 8

DOI: 10.2174/2352096516666230109141037

Price: $65

Abstract

Introduction: Advanced low-power designs have been scaled down to the device parameters that increase single-event multi-node upset in memory elements. This degradation of the stability of the memory elements in aerospace applications is due to the high radiation environment and rapid temperature changes.

Methods: Hence, this paper presents a comprehensive treatment model for hardened storage elements with a soft error resulting in multi-node upset. A novel 12T SRAM memory cell configuration has been proposed, analysed, and simulated using Cadence Virtuoso gpdk 45 nm CMOS technology.

Results: The proposed design counteracts the positive feedback induced due to the charged ion strike, as in past technical literature. The radiation environment has been realized with double exponential current sources, and temperature analysis has been carried out under parametric analysis.

Conclusion: The novel 12T achieves good stability and remains resilient to bit-flip due to ion strikes for a wider range of voltage when the temperature varies from -50°C to 200°C. Moreover, the proposed structure features a lower susceptibility to single event upset, less write and read time, and reduced area compared to the reported RSP 14T.

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[1]
D. Malagón, G. Torrens, J. Segura, and S.A. Bota, "Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment", Microelectron. Reliab., vol. 110, p. 113696, 2020.
[http://dx.doi.org/10.1016/j.microrel.2020.113696]
[2]
L. Lu, T. Yoo, L. Van Loi, and T.T.H. Kim, "An ultra-low power 8T SRAM with vertical read word line and data aware write assist", IEEE Asian Solid-State Circuits Conf. A-SSCC - Proc.
vol. 6, 2018pp. 143-144 [http://dx.doi.org/10.1109/ASSCC.2018.8579292]
[3]
U. Gatti, C. Calligaro, E. Pikhay, and Y. Roizin, "Radiation-hardened techniques for CMOS flash ADC", 21st IEEE Int. Conf. Electron. Circuits Syst. ICECS. 2015, pp. 1-4.
[4]
T.S. Nidhin, A. Bhattacharyya, R.P. Behera, T. Jayanthi, and K. Velusamy, "Understanding radiation effects in SRAM-based field programmable gate arrays for implementing instrumentation and control systems of nuclear power plants", Nucl. Eng. Technol., vol. 49, no. 8, pp. 1589-1599, 2017.
[http://dx.doi.org/10.1016/j.net.2017.09.002]
[5]
S.M. Jahinuzzaman, D.J. Rennie, and M. Sachdev, "A soft error tolerant 10T SRAM bit-cell with differential read capability", IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3768-3773, 2009.
[http://dx.doi.org/10.1109/TNS.2009.2032090]
[6]
L. Atias, A. Teman, R. Giterman, P. Meinerzhagen, and A. Fish, "A low-voltage radiation-hardened 13T SRAM bitcell for ultralow power space applications”, IEEE Trans. Very Large Scale Integr. (VLSI)", Syst., vol. 24, no. 8, pp. 2622-2633, 2016.
[http://dx.doi.org/10.1109/TVLSI.2016.2518220]
[7]
S. Lin, Y-B. Kim, and F. Lombardi, "Analysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset", IEEE Trans. Device Mater. Reliab., vol. 12, no. 1, pp. 68-77, 2012.
[http://dx.doi.org/10.1109/TDMR.2011.2167233]
[8]
J. Guo, L. Zhu, W. Liu, H. Huang, S. Liu, T. Wang, L. Xiao, and Z. Mao, "Novel Radiation-Hardened-by-Design (RHBD) 12T memory cell for aerospace applications in nanoscale CMOS technology”, IEEE Trans. Very Large Scale Integr. (VLSI)", Syst., vol. 25, no. 5, pp. 1593-1600, 2017.
[http://dx.doi.org/10.1109/TVLSI.2016.2645282]
[9]
C.I. Kumar, and B. Anand, "A highly reliable and energy efficient radiation hardened 12T SRAM cell design", IEEE Trans. Device Mater. Reliab., vol. 20, no. 1, pp. 58-66, 2020.
[http://dx.doi.org/10.1109/TDMR.2019.2956601]
[10]
C. Peng, J. Huang, C. Liu, Q. Zhao, S. Xiao, X. Wu, Z. Lin, J. Chen, and X. Zeng, "Radiation-hardened 14T SRAM bitcell with speed and power optimized for space application”, IEEE Trans. Very Large Scale Integr. (VLSI)", Syst., vol. 27, no. 2, pp. 407-415, 2019.
[http://dx.doi.org/10.1109/TVLSI.2018.2879341]
[11]
P. Bikki, and P. Karuppanan, "SRAM cell leakage control techniques for ultra low power application: A survey", Circuits and Systems, vol. 8, no. 2, pp. 23-52, 2017.
[http://dx.doi.org/10.4236/cs.2017.82003]
[12]
P. Yang, X. Ye, Y. Zhao, W. Zhang, S. Huang, Y. Huang, and Y. Wang, "An error detecting scheme with input offset regulation for enhancing reliability of ultralow-voltage SRAM", Microelectron. Reliab., vol. 114, p. 113788, 2020.
[http://dx.doi.org/10.1016/j.microrel.2020.113788]
[13]
A. Islam, and M. Hasan, "Variability aware low leakage reliable SRAM cell design technique", Microelectron. Reliab., vol. 52, no. 6, pp. 1247-1252, 2012.
[http://dx.doi.org/10.1016/j.microrel.2012.01.003]
[14]
R.C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies", IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 305-316, 2005.
[http://dx.doi.org/10.1109/TDMR.2005.853449]
[15]
M. Zhang, and N.R. Shanbhag, "Soft-Error-Rate-Analysis (SERA) methodology", IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., vol. 25, no. 10, pp. 2140-2155, 2006.
[http://dx.doi.org/10.1109/TCAD.2005.862738]
[16]
V. Sharma, S. Vishvakarma, S.S. Chouhan, and K. Halonen, "A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes", Int. J. Circuit Theory Appl., vol. 46, no. 12, pp. 2314-2333, 2018.
[http://dx.doi.org/10.1002/cta.2555]
[17]
S.H. Hsu, Y.Y. Huang, Y.D. Wu, K. Yang, L.H. Lin, and L. Milor, "Extraction of wearout model parameters using on-line test of an SRAM", Microelectron. Reliab., vol. 114, p. 113756, 2020.
[http://dx.doi.org/10.1016/j.microrel.2020.113756]
[18]
A. Bhaskar, "Design and analysis of low power SRAM cells", Innov. Power Adv. Comput. Technol. i-PACT.
pp. 1-5, 2017. [http://dx.doi.org/10.1109/IPACT.2017.8244888]
[19]
H. Nan, and K. Choi, "High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology", IEEE Trans. Circuits Syst. I Regul. Pap., vol. 59, no. 7, pp. 1445-1457, 2012.
[http://dx.doi.org/10.1109/TCSI.2011.2177135]
[20]
P. Bikki, and M. Annapurna, "Analysis of low power novel SRAM design with self-biasing approach for ultra-low power applications", Int. Conf. Microw. Integr. Circuits, Photonics Wirel. Networks.
2019, pp. 269-273 [http://dx.doi.org/10.1109/IMICPW.2019.8933217]
[21]
P. Bikki, "M.K.R.T, M. Annapurna and S. Vujwala, Analysis of low power sram design with leakage control techniques", 2019 TEQIP III Sponsored International Conference on Microwave Integrated Circuits, Photonics and Wireless Networks (IMICPW), Tiruchirappalli, India, p. 2019, pp. 400-404, .
[http://dx.doi.org/10.1109/IMICPW.2019.8933178]

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