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Recent Advances in Electrical & Electronic Engineering

Editor-in-Chief

ISSN (Print): 2352-0965
ISSN (Online): 2352-0973

Research Article

Parallelised Multithreaded Applications on a 4-core Field Programmable Gate Array (FPGA) Architecture

Author(s): George K. Adam*

Volume 15, Issue 3, 2022

Published on: 22 July, 2022

Page: [255 - 264] Pages: 10

DOI: 10.2174/2352096515666220603165247

Price: $65

Abstract

Background: The challenges in real-time multithreading, particularly in the efficiency of multithreaded applications running concurrently on multiple cores, have evolved significantly due to the increase in IoT, cloud and edge computing applications. The continuous increase in cores depth adds further research issues related to the efficiency of such multicore systems and their applications. Therefore, further research is still required.

Multicore systems can achieve higher performance running in parallel multiple multithreaded applications. However, efficient parallelisation of multiple threads among many cores is not an easy task. Field Programmable Gate Arrays (FPGAs) is a preferred technology for the rapid design and experimentation with such architectures, based primarily on softcore processors.

Objectives: The purpose of this research is to investigate the efficiency of running in parallel and concurrently multithreaded applications on a 4-core FPGA multicore architecture.

Methods: The design of a 4-core FPGA architecture is implemented with Nios II/f soft processors on a Cyclone IV series chip, having real-time Linux operating system (OS) support. A multithreaded application with specific compute-intensive tasks is developed in C, and is used to obtain measurements in specific efficiency metrics under different core configurations.

Results: The reliability of the proposed 4-core FPGA architecture is validated against 4-core and 2- core development platforms, respectively, on Raspberry Pi4 and BeagleBone AI single board computers. The results have been analysed and evaluated upon performance metrics, including execution time, response time, speedup, and cores usage. The experimental tests demonstrate the validity and efficiency of the approach to using FPGA for experimentations with multithreaded applications.

Conclusion: The obtained results show that the proposed FPGA architecture stands well both in terms of timing and efficiency metrics. Execution times are about 50% lower, and the average speedup at 21% is fairly close to that of 33% for the Raspberry Pi4, and higher than BeagleBone AI (10%). The proposed measurements approach and evaluation methodology could benefit the design and development of real-time systems utilizing operating systems with real-time support in emerging areas, such as embedded devices in real-time control.

Keywords: FPGA, multicore, multithreaded, real-time, operating systems, performance metrics.

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[1]
P. Hui, and S. Chikkagoudar, "A formal model for real-time parallel computation", First International Workshop on Formal Techniques for Safety-Critical System, vol. 105, pp. 39-55 2012
[http://dx.doi.org/10.4204/EPTCS.105.4]
[2]
A. Ali, and K.H. Kim, "Cluster-based multicore real-time mixed-criticality scheduling", J. Systems Archit., vol. 79, pp. 45-58, 2017.
[http://dx.doi.org/10.1016/j.sysarc.2017.07.001]
[3]
S.Z. Sheikh, and M.A. Pasha, "Energy-efficient multicore scheduling for hard real-time systems - A survey", Trans. Embed. Comput. Syst., vol. 17, no. 6, pp. 1-26, 2018.
[4]
G. García, C. Jara, J. Pomares, A. Alabdo, L. Poggi, and F. Torres, "A survey on FPGA-based sensor systems: Towards intelligent and reconfigurable low-power sensors for computer vision, control and signal processing", Sensors, vol. 14, no. 4, pp. 6247-6278, 2014.
[http://dx.doi.org/10.3390/s140406247] [PMID: 24691100]
[5]
R. Nane, V.M. Sima, C. Pilato, J. Choi, B. Fort, A. Canis, Y.T. Chen, H. Hsiao, S. Brown, F. Ferrandi, J. Anderson, and K. Bertels, "A sur-vey and evaluation of FPGA high-level synthesis tools", IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., vol. 35, no. 10, pp. 1591-1604, 2016.
[http://dx.doi.org/10.1109/TCAD.2015.2513673]
[6]
S. Gandhare, and B. Karthikeyan, "Survey on FPGA architecture and recent applications", In 2019 IEEE International Conference on Vision towards Emerging Trends in Communication and Networking (ViTECoN), p. 2019, pp. 1-4., .30-31 March, 2019,Vellore, India,,
[http://dx.doi.org/10.1109/ViTECoN.2019.8899550]
[7]
C. Satyadhyan, H. Srinidhi, M.K.R. Dadi, and K.M. Aswatha, "Reconfigurable computing: A review", Recent Pat. Comput. Sci., vol. 5, no. 3, pp. 226-237, 2012.
[http://dx.doi.org/10.2174/2213275911205030226]
[8]
J.J.R. Andina, E.T. Arnanz, and M.D.V. Peña, Embedded processors in FPGA architectures.In: FPGAs, Fundamentals, Advanced Fea-tures, and Applications in Industrial Electronics., CRC Press: London, 2017, pp. 59-113.
[http://dx.doi.org/10.1201/9781315162133-3]
[9]
P.P. Chu, Embedded SOPC Design with NIOS II processor and VHDL examples., John Wiley & Sons, Inc., 2011.
[http://dx.doi.org/10.1002/9781118146538]
[10]
M. Daněk, L. Kafka, L. Kohout, J. Sýkora, and R. Bartosinski, UTLEON3: Exploring fine-grain multi-threading in FPGAs., Springer-Verlag: New York, 2013.
[http://dx.doi.org/10.1007/978-1-4614-2410-9]
[11]
O. Mencer, D. Allison, E. Blatt, M. Cummings, M.J. Flynn, J. Harris, C. Hewitt, Q. Jacobson, M. Lavasani, M. Moazami, H. Murray, M. Nikravesh, A. Nowatzyk, M. Shand, and S. Shirazi, "The history, status, and future of FPGAs: Hitting a nerve with field-programmable gate arrays", ACM Queue, vol. 18, no. 3, pp. 71-82, 2020.
[http://dx.doi.org/10.1145/3411757.3411759]
[12]
A. Ismail, and L. Shannon, "FUSE: Front-end user framework for O/S abstraction of hardware accelerators In", 2011 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, 1-3 May, 2011, p. Salt Lake City, UT: USA, 2011, pp. 170-177, .
[http://dx.doi.org/10.1109/FCCM.2011.48]
[13]
S. Kakade, and H. Shahnasser, “Implementation of a real time operating system on Altera’s cyclone IV FPGA”, In 2nd International Con-ference on Digital Enterprise and Information Systems., DEIS: Kuala Lumpur, Malaysia, 2013, pp. 1-11.
[14]
J. Pereira, D. Oliveira, S. Pinto, N. Cardoso, V. Silva, T. Gomes, J. Mendes, and P. Cardoso, "Co-designed FreeRTOS deployed on FPGA In", 2014 IEEE Brazilian Symposium on Computing Systems Engineering, 3-7 Nov, 2014, p. Manaus, Brazil, 2014, pp. 121-125, .
[http://dx.doi.org/10.1109/SBESC.2014.11]
[15]
S. Zhu, "Hardware implementation based on FPGA of semaphore management in μC/OS-II real-time operating system", Int. J. Grid Util. Comput., vol. 6, no. 3-4, pp. 192-199, 2015.
[http://dx.doi.org/10.1504/IJGUC.2015.070677]
[16]
G.K. Adam, "Real-time performance and response latency measurements of Linux kernels on single-board computers", Computers, vol. 10, no. 5, p. 64, 2021.
[http://dx.doi.org/10.3390/computers10050064]
[17]
M. Baklouti, and M. Abid, "Multi-softcore architecture on FPGA", Int. J. Reconfigurable Comput., vol. 2014, pp. 1-13, 2014.
[http://dx.doi.org/10.1155/2014/979327]
[18]
A. Podobas, K. Sano, and S. Matsuoka, "A survey on coarse-grained reconfigurable architectures from a performance perspective", IEEE Access, vol. 8, pp. 146719-146743, 2020.
[http://dx.doi.org/10.1109/ACCESS.2020.3012084]
[19]
L. Shannon, E. Matthews, N. Doyle, and A. Fedorova, "Performance monitoring for multicore embedded computing systems on FPGAs In", 2015 2nd International Workshop on FPGAs for Software Programmers, p. London, United Kingdom, 2015, pp. 68-72, .
[20]
R.K. Pal, K. Paul, and S. Prasad, "ReKonf: Dynamically reconfigurable multiCore architecture", J. Parallel Distrib. Comput., vol. 74, no. 11, pp. 3071-3086, 2014.
[http://dx.doi.org/10.1016/j.jpdc.2014.05.007]
[21]
S. Prasad, "Program execution on reconfigurable multicore architectures In", 2016 9th Workshop on Programming Language Approaches to Concurrency- and Communication-C Entric Software, p. Eindhoven, The Netherlands, 2016, pp. 83-91, .
[http://dx.doi.org/10.4204/EPTCS.211.9]
[22]
X. Iturbe, K. Benkrid, C. Hong, A. Ebrahim, R. Torrego, and T. Arslan, "Microkernel architecture and hardware abstraction layer of a reliable reconfigurable real-time operating system (R3TOS)", ACM Trans. Reconfig. Technol. Syst., vol. 8, no. 1, pp. 1-35, 2015.
[http://dx.doi.org/10.1145/2629639]
[23]
Wikipedia Contributors. "uClinux". [Online]. Available from: https://en.wikipedia.org/wiki/%CE%9CClinux (Accessed on May 21, 2022).
[24]
FreeRTOS, Available from: www.freertos.org (Accessed on May 21, 2022).
[25]
O. Hahm, E. Baccelli, H. Petersen, and N. Tsiftes, "Operating systems for low-end devices in the internet of things: A survey", IEEE Internet Things J., vol. 3, no. 5, pp. 720-734, 2016.
[http://dx.doi.org/10.1109/JIOT.2015.2505901]
[26]
E. Matthews, L. Shannon, and A. Fedorova, "Shared memory multicore microblaze system with SMP linux support", ACM Trans. Reconfig. Technol. Syst., vol. 9, no. 4, pp. 1-22, 2016.
[http://dx.doi.org/10.1145/2870638]
[27]
A. Aysu, S. Gaddam, H. Mandadi, C. Pinto, L. Wegryn, and P. Schaumont, A design method for remote integrity checking of complex PCBs.In., Design, Automation and Test in Europe Conference and Exhibition: Dresden, Germany, 2016, pp. 1517-1522.
[28]
A. Musaddiq, Y.B. Zikria, O. Hahm, H. Yu, A.K. Bashir, and S.W. Kim, "A survey on resource management in IoT operating systems", IEEE Access, vol. 6, pp. 8459-8482, 2018.
[http://dx.doi.org/10.1109/ACCESS.2018.2808324]
[29]
S. Saha, A. Chakrabarti, and R. Ghosh, "Exploration of multithread processing on XILKERNEL for FPGA based embedded systems", In", 2013 IEEE 19th International Conference on Control Systems and Computer Science, 29-31 May, 2013, p. Bucharest, Romania, 2013, pp. 58-65, .
[http://dx.doi.org/10.1109/CSCS.2013.47]
[30]
P.G. Zaykov, and G. Kuzmanov, "Multithreading on reconfigurable hardware: An architectural approach", Microprocess. Microsyst., vol. 36, no. 8, pp. 695-704, 2012.
[http://dx.doi.org/10.1016/j.micpro.2012.05.005]
[31]
T. Gomes, P. Garcia, S. Pinto, J. Monteiro, and A. Tavares, "Bringing hardware multithreading to the real-time domain", IEEE Embed. Syst. Lett., vol. 8, no. 1, pp. 2-5, 2016.
[http://dx.doi.org/10.1109/LES.2015.2486384]
[32]
Intel Corporation, Nios II Processor with Memory Management Unit Design Example, 2021. Available from: https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-mmu.html (Accessed on May 21, 2022).
[33]
GitHub, Inc., Linux Development Repository for SOCFPGA, 2021. Available from: https://github.com/altera-opensource/linux-socfpga (Accessed on May 21, 2022).
[34]
POSIX, Available from: https://en.wikipedia.org/wiki/POSIX (Accessed on May 21, 2022).
[35]
The Linux Foundation Wiki, Real Time Linux, 2021. Available from: https://wiki.linuxfoundation.org/realtime/start (Accessed on May 21, 2022).
[36]
"Zynq UltraScale+ MPSoC, heterogeneous multiprocessing platform for broad range of embedded applications", Available from: www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html (Accessed on May 21, 2022).

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