Abstract
This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter (DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.
Keywords: Flash ADC(Analog-to-digital converter), two-step method, high resolution, low area, comparator, MUX, high-speed DAC, encoder.
Graphical Abstract
[1]
Lee, W-T.; Huang, P-H.; Liao, Y-Z.; Hwang, Y-S. A new low power flash ADC using multiple-selection method. 2007 IEEE Conference on Electron Devices and Solid-State Circuits, 2007, pp. 341-344.
[http://dx.doi.org/10.1109/EDSSC.2007.4450132]
[http://dx.doi.org/10.1109/EDSSC.2007.4450132]
[2]
Lin, J.; Mano, I.; Miyahara, M.; Matsuzawa, A. Ultralow-voltage
high-speed flash ADC design strategy based on FoM-delay product.
IEEE transactions on very large scale integration (VLSI) systems;
2014, 23(8), pp. 1518-1527..
[3]
Hussain, S.; Kumar, M. Design of an efficient 8-bit flash ADC for optical communication receivers. 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016, pp. 449-453.
[http://dx.doi.org/10.1109/ICEEOT.2016.7755560]
[http://dx.doi.org/10.1109/ICEEOT.2016.7755560]
[4]
Chung, Y-H.; Wu, J-T. A 16-mW 8-bit 1-GS/s digital-sub ranging ADC in 55-nm CMOS. IEEE Transactions on Very Large Scale Integration (VLSI). Systems, 2014, 23(3), 557-566.
[5]
Megha, R.; Pradeepkumar, K.A. Implementation of low power flash ADC by reducing comparators. 2014 International Conference on Communication and Signal Processing, 2014, pp. 443-447.
[http://dx.doi.org/10.1109/ICCSP.2014.6949880]
[http://dx.doi.org/10.1109/ICCSP.2014.6949880]
[6]
Im Lee, J.; Song, J-I. Flash ADC architecture using multiplexers to
reduce a preamplifier and comparator count. 2013 IEEE International
Conference of IEEE Region 10 (TENCON 2013), 2013, pp.
1-4..
[7]
Rahul, P.V.; Anusha, A. Kulkarni; Sohail, Sankanur; Raghavendra, M. Reduced comparators for low power flash ADC using tsmc018. 2017 International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS), 2017, pp. 1-5.
[8]
Bhargava, C.; Mody, V.; Rathour, N.; Bansal, S. MUX based flash ADC for the reduction in the number of comparators. 2018 International Conference on Intelligent Circuits and Systems (ICICS), 2018, pp. 52-57.
[9]
Kanan, R. ; François, Kaess; Declercq, M. A 640 mW high accuracy
8-bit 1 GHz flash ADC encoder. ISCAS'99. Proceedings of the
1999 IEEE International Symposium on Circuits and Systems VLSI
(Cat. No. 99CH36349), 1999, 2, pp. 420-423..
[10]
Weaver, S.; Hershberg, B.; Kurahashi, P.; Knierim, D.; Moon, U-K. Stochastic flash analog-to-digital conversion. IEEE Trans. Circuits Syst. I Regul. Pap., 2010, 57(11), 2825-2833.
[http://dx.doi.org/10.1109/TCSI.2010.2050225]
[http://dx.doi.org/10.1109/TCSI.2010.2050225]
[11]
Chahardori, Mohammad; Sharifkhani, Mohammad IEEE Trans. Circuits Syst. I Regul. Pap., 2013, 60(9), 2285-2297.
[http://dx.doi.org/10.1109/TCSI.2013.2246206]
[http://dx.doi.org/10.1109/TCSI.2013.2246206]
[12]
Wang, L.; LaCroix, M-A.; Carusone, A.C.A. 4-GS/s single-channel reconfigurable folding flash ADC for wireline applications in 16-nm FinFET. IEEE Trans. Circuits Syst., II Express Briefs, 2017, 64(12), 1367-1371.
[http://dx.doi.org/10.1109/TCSII.2017.2726063]
[http://dx.doi.org/10.1109/TCSII.2017.2726063]
[13]
Siqiang, F.; Tang, H.; Zhao, H.; Wang, X.; Wang, A.; Zhao, B.; Zhang, G.G. Enhanced offset averaging technique for flash ADC design. Tsinghua Sci. Technol., 2011, 16(3), 285-289.
[http://dx.doi.org/10.1016/S1007-0214(11)70041-4]
[http://dx.doi.org/10.1016/S1007-0214(11)70041-4]
[14]
Jayakumar, A.; Vishnu, K. A 7-bit 500-MHz flash ADC. 2014 First International Conference on Computational Systems and Communications (ICCSC), 2014, pp. 75-79.
[http://dx.doi.org/10.1109/COMPSC.2014.7032624]
[http://dx.doi.org/10.1109/COMPSC.2014.7032624]
[15]
Patil, H.; Raghavendra, M. Low power dynamic comparator for 4—bit Flash ADC. 2016 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), 2016, pp. 1-4.
[http://dx.doi.org/10.1109/ICCIC.2016.7919550]
[http://dx.doi.org/10.1109/ICCIC.2016.7919550]
[16]
Couto-Pinto, A.; Fernandes, J.R.; Piedade, M.; Silva, M.M. A flash ADC tolerant to high offset voltage comparators. Circuits Syst. Signal Process., 2017, 36(3), 1150-1168.
[http://dx.doi.org/10.1007/s00034-016-0350-3]
[http://dx.doi.org/10.1007/s00034-016-0350-3]
[17]
Abumurad, A.; Choi, K. Design procedure and selection of TIQ comparators for flash ADCs. Circuits Syst. Signal Process., 2018, 37(2), 500-531.
[http://dx.doi.org/10.1007/s00034-017-0574-x]
[http://dx.doi.org/10.1007/s00034-017-0574-x]
[18]
Kumar, U. CMOS customization of comparator for hispeed flash ADC., Journal of circuits and electronics, 2017, 2. Available from:. http://www.iaras.org/iaras/journals/
[19]
Suruchi, Tiwari; Abhishek, Kumar 4 bit flash adc using tiq comparator.I J C T A. International Science Press, 2016, 9(11), 5235-5242.
[20]
Dastagiri, Nadhindla Bala; Kakarla, Hari Kishore; Vinit, Kumar
Gunjan; Shaik, Fahimuddin Design of a low-power low-kickback-noise latched dynamic comparator for cardiac implantable medical device applications. In: Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications; Springer: Singapore, 2018; pp. 637-645.
[21]
Ahmed, G.; Baghel, R.K. Design Of 6-bit flash analog to digital converter using variable switching voltage cmos comparator. International Journal of VLSI Design & Communication Systems, 2014, 5(3), 25.
[http://dx.doi.org/10.5121/vlsic.2014.5303]
[http://dx.doi.org/10.5121/vlsic.2014.5303]
[22]
Lam, H-M.; Tsui, C-Y. A MUX-based high-performance single-cycle CMOS comparator. IEEE Trans. Circuits Syst., II Express Briefs, 2007, 54(7), 591-595.
[http://dx.doi.org/10.1109/TCSII.2007.899856]
[http://dx.doi.org/10.1109/TCSII.2007.899856]
[23]
Nagar, Rajesh Kumar; Chandrawat, U. B. S. Design of a 3.0 MSPS, 2.5 V, 0.25 μm, 4-Bit Flash ADC based on TIQ comparator..
[24]
Senthil Sivakumar, M.; Sowmya Priya, M. Design and analysis of a comparator for flash ADC., International journal of recent technology and engineering (IJRTE), 2019, 7(5S4).
[25]
Khorami, A. Baraani Dastjerdi, Mahmood; Fotowat Ahmadi, Ali A low-power high-speed comparator for analog to digital converters. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 2010-2013.
[http://dx.doi.org/10.1109/ISCAS.2016.7538971]
[http://dx.doi.org/10.1109/ISCAS.2016.7538971]
[26]
Melikyan Vazgen, Sh.; Vardan, P. Grigoryants; Mkhitaryan, Artur
Kh.; Petrosyan, Gegham A.; Hayrapetyan, Andranik K.; Avetisyan,
Zaven M.; Gharibyan, Simon H.; Beglaryan, Nune H. Low power,
low offset, area efficient comparator design in nanoscale CMOS
technology. 2018 IEEE East-West Design & Test Symposium
(EWDTS), 2018, pp. 1-5..
[27]
Rahman, L.F.; Reaz, M.B.; Yin, C.C.; Ali, M.A.; Marufuzzaman, M. Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process. PLoS One, 2014, 9(10), e108634.
[http://dx.doi.org/10.1371/journal.pone.0108634] [PMID: 25299266]
[http://dx.doi.org/10.1371/journal.pone.0108634] [PMID: 25299266]
[28]
Joy, R.S. ; Zacharia, Reneesh C. Low power hardware efficient
comparator using full swing 3T XNOR. International journal of
recent technology and engineering (IJRTE), 2019, 8(1S4).
[29]
Gandhi, P.P.; Devashrayee, N.M. A novel low offset low power CMOS dynamic comparator. Analog Integr. Circuits Signal Process., 2018, 96(1), 147-158.
[http://dx.doi.org/10.1007/s10470-018-1166-9]
[http://dx.doi.org/10.1007/s10470-018-1166-9]
[30]
Mongre, R.; Gurjar, R.C. Design of Low Power & High-Speed Comparator with 0.18 µm Technology for ADC Application. Int. J. Eng. Res. Appl., 2014, 4, 146-153.
[31]
Babayan-Mashhadi, Samaneh ; Lotfi, Reza Analysis and design of a
low-voltage low-power double-tail comparator.IEEE transactions
on very large scale integration (VLSI) systems; , 2013, 22, pp.
(2)343-352.
[32]
Razavi, B.; Wooley, B.A. Design techniques for high-speed, high-resolution comparators. IEEE J. Solid-State Circuits, 1992, 27(12), 1916-1926.
[http://dx.doi.org/10.1109/4.173122]
[http://dx.doi.org/10.1109/4.173122]
[33]
Mahatma, Himanshu; Mehra, Rajesh Low power multiplexer design
using modified DCVSL logic. IOSR journal of VLSI and signal
processing (IOSR-JVSP), 6(3), 13-17.
[34]
Chary, Udary Gnaneshwara; Aman KumarKuna, Sateesh Design of low voltage low power CMOS analog multiplexer for biomedical applications., International journal of engineering and advanced technology (IJEAT), 1992, 3, 21-24..
[35]
Mahima, Singh; Gautam, Dolly; Tomar, D. S. S. Designing and optimizations of low power multiplexer using CMOS device modeling. International journal of advanced research in computer and communication engineering., 2007, 7(1), 2319-5940.
[36]
Pandey, Saumya ; Dr. Nidhi, Goel A power-efficient 2:1 multiplexer
design for low power VLSI applications. International journal of
advanced research in electronics and communication engineering
(IJARECE), 2016, 5(1).
[38]
Sall, E.; Vesterbacka, M. Thermometer-to-binary decoders for flash
analog-to-digital converters. 2007 18th European Conference on
Circuit Theory and Design, 2007, , pp. 240-243..
[http://dx.doi.org/10.1109/ECCTD.2007.4529581]
[http://dx.doi.org/10.1109/ECCTD.2007.4529581]
[39]
Deepika, Kasthuri; Naresh, K. Design of efficient multiplexer based encoder for flash-adc using 120nmcmos technology. Int. J. Technol. Res. Eng., 2015, 2(12), 2347-4718.
[40]
Van Hieu, B.; Choi, S. ; Seon, Jongkug; cheol Oh, Young; Park,
Chongdae; Jaehyoun, Park; Kim, Hyunwook; Jeong, Taikyeong A
new approach to the thermometer-to-binary encoder of flash ADCbubble
error detection circuit. 2011 IEEE 54th International Midwest
Symposium on Circuits and Systems (MWSCAS), 2011, pp. 1-
4..
[41]
Zachariah, V. ; Sudirpatnai kun, V.Y.S.S.; Mouli, K.; Manikantasai,
B. Cmos full adder and multiplexer based encoder for lowresolution
flash Adc. IOSR journal of electronics and communication
engineering (IOSR-JECE), 2017, 12(2), 20-27..
[42]
Jogdand, R.R.; Dakhole, P.K. Prachi, Palsodkar Low power flash ADC using multiplexer based encoder. 2017 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS), 2017, pp. 1-5.
[43]
Kumar, S.; Suman, M.K.; Baishnab, K.L. A novel approach to the
thermometer-to-binary encoder of flash ADCs-bubble error correction
circuit. 2014 2nd International Conference on Devices, Circuits
and Systems (ICDCS), 2014, pp. 1-6..
[44]
Mayur, S.M. Design of novel multiplexer based thermometer to
binary code encoder for 4-bit flash ADC. 2017 2nd IEEE International
Conference on Recent Trends in Electronics, Information &
Communication Technology (RTEICT), 2017, pp. 1006-1100.
http://dx.doi.org/10.1109/RTEICT.2017.8256750.
[45]
Gupta, Y.; Saini, S. Thermometer to gray encoders.In: Performance optimization techniques in analog, mixed-signal, and radio-frequency circuit design; IGI Global, 2015, pp. 323-335.
[http://dx.doi.org/10.4018/978-1-4666-6627-6.ch013]
[http://dx.doi.org/10.4018/978-1-4666-6627-6.ch013]
[46]
Mayank, Mrinal; Jaijee, Jagatbir S.; Bhulania, Paurush; Mehra, Anu; Rana, Haneet Khanna, Shweta Study and designing of fourth order BECCircuitforflash analog to digital converter using MUX based encoder. Indian J. Sci. Technol., 2017, 10(18)
[http://dx.doi.org/10.17485/ijst/2017/v10i18/106370]
[http://dx.doi.org/10.17485/ijst/2017/v10i18/106370]
[47]
Huang, H.; Heilmeyer, J.; Grözing, M.; Berroth, M.; Leibrich, J.; Rosenkranz, W. An 8-bit 100-GS/s distributed DAC in 28-nm CMOS for optical communications. IEEE Trans. Microw. Theory Tech., 2015, 63(4), 1211-1218.
[http://dx.doi.org/10.1109/TMTT.2015.2403846]
[http://dx.doi.org/10.1109/TMTT.2015.2403846]
[48]
Schmidt, C.; Kottke, C.; Jungnickel, V.; Freund, R. High-speed digital-to-analog converter concepts. In: Next-generation optical communication: Components, sub-systems, and systems VI; International
Society for Optics and Photonics, 2017; 10130, p.
101300N..
[49]
Bandali, M.; Hassanzadeh, A. Ghashghaie, Masoume; Hashemipour, Omid An 8-bit ultra-low-power, low-voltage current steering DAC utilizing a new segmented structure. J. Circuits Syst. Comput., 2019, 28(10), 1950172.
[http://dx.doi.org/10.1142/S021812661950172X]
[http://dx.doi.org/10.1142/S021812661950172X]
[50]
Muqeeta, M.A.; Habeebaand, M.S.; Zeeshan, Aa. Static and dynamic
parameter evaluation of 8-bit multiplying digital-analog
converter (MDAC) using 3-NMOS per bit conversion"See discussions,
stats, and author profiles for this publication. 2019. Available
from: . https://www.researchgate.net/publication/335652099
[http://dx.doi.org/10.13140/RG.2.2.15717.35043/1]
[http://dx.doi.org/10.13140/RG.2.2.15717.35043/1]
[51]
Kuivalainen, Pekka AÅberg, Markku Low power high-speed neuron MOS digital-to-analog converters with minimal silicon area. Analog Integr. Circuits Signal Process., 2001, 26(1), 53-61.
[http://dx.doi.org/10.1023/A:1008370118221]
[http://dx.doi.org/10.1023/A:1008370118221]
[52]
Chen, P.; Shen, Y-S.; Chen, C-C. A low-cost low-power CMOS time-to-digital converter based on pulse stretching. IEEE Trans. Nucl. Sci., 2006, 53(4), 2215-2220.
[http://dx.doi.org/10.1109/TNS.2006.876051]
[http://dx.doi.org/10.1109/TNS.2006.876051]
[53]
Juanda, F.N.U.; Shu, W.; Joseph, S. Chang A 10-GS/s 4-bit single-core digital-to-analog converter for cognitive ultrawideband. IEEE Trans. Circuits Syst., II Express Briefs, 2016, 64(1), 16-20.
[http://dx.doi.org/10.1109/TCSII.2016.2551544]
[http://dx.doi.org/10.1109/TCSII.2016.2551544]
[54]
Chander, K.; Choudhry, S. 65nm low power digital to analog converter
for CUWB. 2018 2nd International Conference on Trends in
Electronics and Informatics (ICOEI), 2018, pp. 610-614..
[http://dx.doi.org/10.1109/ICOEI.2018.8553815]
[http://dx.doi.org/10.1109/ICOEI.2018.8553815]
[55]
Aiello, O.; Crovetti, P.S.; Alioto, M. Fully synthesizable low-area digital-to-analog converter with graceful degradation and dynamic power-resolution scaling. IEEE Trans. Circuits Syst. I Regul. Pap., 2019, 66(8), 2865-2875.
[http://dx.doi.org/10.1109/TCSI.2019.2903464]
[http://dx.doi.org/10.1109/TCSI.2019.2903464]
[56]
Yoon, D-H.; Jung, D-K.; Jung, B-Y.; Choi, J-M.; Jo, Y-J.; Lee, S.; Lee, W.; Baek, K-H.L.W-D.EM: Designing a low power digital-to-analog converter using lightweight dynamic element matching technique. IEEE Access, 2019, 7, 112617-112628.
[http://dx.doi.org/10.1109/ACCESS.2019.2935259]
[http://dx.doi.org/10.1109/ACCESS.2019.2935259]
[57]
Mulder, Jan; Ward, Christopher M.; Lin, Chi-Hung; Kruse, David;; Westra, Jan R.; Lugthart, Marcel; Arslan, Erol; van de Plassche, Rudy J. Bult, Klaas. IEEE J. Solid-State Circuits, 2004, 39(12), 2116-2125.
[http://dx.doi.org/10.1109/JSSC.2004.836235]
[http://dx.doi.org/10.1109/JSSC.2004.836235]
[58]
Lim, Jaehyun ; Choi, Kyusun CMOS analog addition/subtraction. Pennstate mixed-signal chip design lab, Cse 577,. 2011.
[59]
Ohhata, K.A. 2.3-mW, 1-GHz, 8-bit fully time-based two-step ADC using a high-linearity dynamic VTC. IEEE J. Solid-State Circuits, 2019, 54(7), 2038-2048.
[http://dx.doi.org/10.1109/JSSC.2019.2907401]
[http://dx.doi.org/10.1109/JSSC.2019.2907401]
[60]
Greenley, Brandon; Veith, Raymond; Dong-young, Chang; Moon, Un-Ku . A low-voltage 10-bitcmosdacin0.01-Mm2 die area. IEEE
transactions on circuits and systems—Ii: Express briefs; 2005, 52(5). Digital object identifier.
[http://dx.doi.org/10.1109/TCSII.2005.843595]
[http://dx.doi.org/10.1109/TCSII.2005.843595]
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