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ISSN (Print): 2352-0965
ISSN (Online): 2352-0973

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General Research Article

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-gate Bias in a Nanometer CMOS Inverter

Author(s): Kai Zhang, Weifeng Lu*, Peng Si, Zhifeng Zhao and Tianyu Yu

Volume 14, Issue 3, 2021

Published on: 08 December, 2020

Page: [339 - 346] Pages: 8

DOI: 10.2174/2352096513666201208102615

Price: $65

Abstract

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits.

Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology.

Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG.

Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover they are also insensitive to channel doping with back-gate bias.

Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Keywords: Nanometer CMOS, timing characteristic, back-gate bias, random dopant fluctuation, CMOS inverter, RDF-induced timing.

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[1]
K. Zhang, Y.N. Chen, Y. Dong, Z.Q. Xie, Z.Z. Zhao, P. Si, T.Y. Yu, L. Dai, and W.F. Lü, "Effect of random channel dopants on timing variation for nanometer CMOS inverters", In: Proceedings of International Conference on Electronics Technology, Chengdu, China, 2019, pp. 208-212.
[http://dx.doi.org/10.1109/ELTECH.2019.8839501]
[2]
X. Wang, F. Adamu-Lema, B. Cheng, and A. Asenov, "Geometry, temperature, and body bias dependence of statistical variability in 20-nm bulk CMOS technology: A comprehensive simulation analysis", IEEE Trans. Electron Dev., vol. 60, pp. 547-1554, 2013.
[http://dx.doi.org/10.1109/TED.2013.2254490]
[3]
A.E. Solis, J.C. Tinoco, A.G. Martinez-Lopez, M.A. Reyes-Barranca, A. Cerdeira, and J.P. Raskin, "Parasitic gate resistance impact on triple-gate FinFET CMOS inverter", IEEE Trans. Electron Dev., vol. 63, pp. 2635-2642, 2016.
[http://dx.doi.org/10.1109/TED.2016.2558580]
[4]
N. Ali, D. Dheer, S. Paliwal, and C. Periasamy, "TCAD analysis of variation in channel doping concentration on 45nm Double-Gate MOSFET parameters", In: Annual IEEE India Conference (INDICON), New Delhi, India, 2016, pp. 1-6.
[5]
W.L. Sung, and Y. Li, "DC/AC/RF characteristic fluctuations induced by various random discrete dopants of gate-all-around silicon nanowire n-MOSFETs", IEEE Trans. Electron Dev., vol. 65, pp. 1-9, 2018.
[http://dx.doi.org/10.1109/TED.2018.2822484]
[6]
K.J. Kuhn, "Considerations for ultimate CMOS Scaling", IEEE Trans. Electron Dev., vol. 59, pp. 1813-1828, 2012.
[http://dx.doi.org/10.1109/TED.2012.2193129]
[7]
J.P. Colinge, "Multiple-gate SOI MOSFETs", Solid-State Electron., vol. 48, pp. 897-905, 2004.
[http://dx.doi.org/10.1016/j.sse.2003.12.020]
[8]
S. Majzoub, "Reducing random-dopant fluctuation impact using footer transistors in many-core systems", Integration, VLSI J., vol. 48, pp. 46-54, 2015.
[http://dx.doi.org/10.1016/j.vlsi.2014.06.005]
[9]
T. Numata, M. Noguchi, and S.I. Takagi, "Reduction in threshold voltage fluctuation in fully-depleted SOI MOSFETs with back gate control", Solid-State Electron., vol. 48, pp. 979-984, 2004.
[http://dx.doi.org/10.1016/j.sse.2003.12.018]
[10]
S.V. Kumar, C.H. Kim, and S.S. Sapatnekar, "Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits", IEEE T VLSI Syst., vol. 19, pp. 603-614, 2011.
[11]
R. Faraji, and H.R. Naji, "Adaptive technique for overcoming performance degradation due to aging on 6T SRAM cells", IEEE Trans. Device Mater. Reliab., vol. 14, pp. 1031-1040, 2014.
[http://dx.doi.org/10.1109/TDMR.2014.2360779]
[12]
H. Mostafa, M. Anis, and M. Elmasry, "Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells", IEEE Transact. Circ. Syst. I, vol. 58, pp. 2859-2871, 2011.
[http://dx.doi.org/10.1109/TCSI.2011.2158708]
[13]
W.T. Chang, C.T. Shih, J.L. Wu, and S.W. Lin, "Back-biasing to performance and reliability evaluation of UTBB FDSOI, Bulk FinFETs, and SOI FinFETs", IEEE Trans. NanoTechnol., vol. 17, pp. 36-40, 2017.
[http://dx.doi.org/10.1109/TNANO.2017.2706265]
[14]
Jaksic, “Enhancing 6T SRAM cell stability by back gate biasing techniques for10nm SOI FinFETs under process and environmental variations”, Mixed Design Integ. Circ. Syst., IEEE, pp. 103-108, 2012.
[15]
W. Wu, H. Wu, J.Y. Zhang, M.W. Si, Y. Zhao, and P.D. Ye, "Carrier mobility enhancement by applying back-gate bias in Ge-on-insulator MOSFETs", IEEE Electron Device Lett., vol. 39, pp. 176-179, 2017.
[http://dx.doi.org/10.1109/LED.2017.2787023]
[16]
E.G. Marin, F.G. Ruiz, A. Godoy, L.M. Tienda-Luna, C. Martinez-Blanque, and F. Gami, "Impact of the back-gate biasing on trigate MOSFET electron mobility", IEEE Trans. Electron Dev., vol. 62, pp. 224-227, 2015.
[http://dx.doi.org/10.1109/TED.2014.2367574]
[17]
D. Gola, B. Singh, and P.K. Tiwari, "Subthreshold modeling of tri-gate junctionless transistors with variable channel edges and substrate bias effects", IEEE Trans. Electron Dev., vol. 65, pp. 1663-1671, 2018.
[http://dx.doi.org/10.1109/TED.2018.2809865]
[18]
Y.K. Lin, P. Kushwaha, H. Agarwal, H.L. Chang, J.P. Duarte, A.B. Sachid, S. Khandelwal, S. Salahuddin, and C.M. Hu, "Modeling of back-gate effects on gate-induced drain leakage and gate currents in UTB SOI MOSFET", IEEE Trans. Electron Dev., vol. 64, pp. 3986-3990, 2017.
[http://dx.doi.org/10.1109/TED.2017.2735455]
[19]
B.K. Esfeh, V. Kilchytska, B. Parvais, N. Planes, M. Haond, D. Flandre, and J.P. Raskin, "Back-gate bias effect on UTBB-FDSOI non-linearity performance", In: 2017 47th European Solid-State Device Research Conference (ESSDERC), 2017, pp. 148-151.
[http://dx.doi.org/10.1109/ESSDERC.2017.8066613]
[20]
L. Wang, C. Wu, L. Feng, A. Chang, and Y. Lian, "A low-power forward and reverse body bias generator in CMOS 40 nm", IEEE T VSLI Syst., vol. 26, pp. 1403-1407, 2018.
[21]
K. Seunghoon, J. Gwanghyeon, and H. Songcheol, "Study on dynamic body bias controls of RF CMOS cascode power amplifier", IEEE Microw. Wirel. Compon. Lett., vol. 28, pp. 705-707, 2018.
[http://dx.doi.org/10.1109/LMWC.2018.2849209]
[22]
M.K. Md Arshad, S. Makovejev, S. Olsen, F. Andrieu, J.P. Raskin, D. Flandre, and V. Kilchytska, "UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime", Solid-State Electron., vol. 90, pp. 56-64, 2013.
[http://dx.doi.org/10.1016/j.sse.2013.02.051]
[23]
W.F. Lü, and L.L. Sun, "Compact modeling of response time and random-dopant-fluctuation-induced variability in nanoscale CMOS inverter", Microelectronics J., vol. 45, pp. 678-682, 2014.
[http://dx.doi.org/10.1016/j.mejo.2014.03.019]
[24]
Y. Li, C.H. Hwang, and T.Y. Li, "Random-dopant-induced variability in nano-CMOS devices and digital circuits", IEEE Trans. Electron Dev., vol. 56, pp. 1588-1597, 2009.
[http://dx.doi.org/10.1109/TED.2009.2022692]
[25]
H. Jooypa, and D. Dideban, "Impact analysis of statistical variability on the accuracy of a propagation delay time compact model in nano-CMOS technology", J. Comput. Electron., vol. 17, pp. 1-13, 2017.
[26]
S. Mukhopadhyay, K. Kim, and C.T. Chuang, "Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies", In: Proceedings of the 2007 International Symposium on Low Power Electronics And Design (ISLPED07), 2007, pp. 20-25.
[http://dx.doi.org/10.1145/1283780.1283786]
[27]
Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M.L. Jiang, and Y. Lnoue, "Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies", IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., vol. 29, pp. 250-260, 2010.
[http://dx.doi.org/10.1109/TCAD.2009.2035539]

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