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ISSN (Print): 2352-0965
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Research Article

Investigation and Reliability Analysis of Fifteen-level Asymmetrical Multilevel Inverter Topology using Nearest Level Control Technique with low Component Count

Author(s): Abeera D. Roy* and Chandrahasan Umayal

Volume 14, Issue 2, 2021

Published on: 20 October, 2020

Page: [198 - 209] Pages: 12

DOI: 10.2174/2352096513999201020213639

Price: $65

Abstract

Background: In multi-level inverters (MLI), as the number of levels increases, there is a proportionate increase in the count of the semiconductor devices that are employed.

Methods: An asymmetrical multi-level inverter topology using a bidirectional switch is presented, which employs a lesser number of power electronic devices to produce fifteen levels at the output voltage. The Nearest Level Modulation (NLM) technique is used to generate the switching pulses and reliability analysis is performed using Markov reliability methodology. The operating principle of the proposed MLI and its performance abilities are verified through MATLAB/Simulink and a prototype is developed to provide the experimental results.

Results: Total Harmonic Distortion (THD) is computed for the proposed MLI for different types of loads in the simulation environment as well as in the developed hardware prototype. The fifteen level is achieved by using only 9 switches and 3 DC sources in comparison to the 28 switches and 6 DC sources required by the traditional cascaded H-bridge inverter.

Conclusion: The simulation and hardware results confirm the suitability of the proposed fifteen level MLI as the total component count and the requirement of DC sources reduces considerably.

Keywords: MLI, asymmetrical, reliability analysis, Nearest Level Modulation (NLM), Total Harmonic Distortion (THD), cascaded H-bridge inverter.

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[1]
J. Rodriguez, J-S. Lai, and F.Z. Peng, "Multilevel inverters: A survey of topologies, controls, and applications", IEEE Trans. Ind. Electron., vol. 49, pp. 724-738, 2002.
[http://dx.doi.org/10.1109/TIE.2002.801052]
[2]
L. Franquelo, J. Rodriguez, J. Leon, S. Kouro, R. Portillo, and M. Prats, "The age of multilevel converters arrives", IEEE Ind. Electron. Mag., vol. 2, pp. 28-39, 2008.
[http://dx.doi.org/10.1109/MIE.2008.923519]
[3]
I. Colak, E. Kabalci, and R. Bayindir, "Review of multilevel voltage source inverter topologies and control schemes", Energy Convers. Manage., vol. 52, pp. 1114-1128, 2011.
[http://dx.doi.org/10.1016/j.enconman.2010.09.006]
[4]
E. Babaei, M. Sarbanzadeh, M.A. Hosseinzadeh, and C. Buc-cella, ""A new topology for cascaded multilevel inverters with reduced number of power electronic switches", In: 2016 7th Power Electronics and Drive Systems Technologies Conference (PEDSTC), Tehran, Iran, 2016, pp. 165-170.
[5]
A.D. Roy, "A review of various multilevel inverter topologies with reduced component count", In: Int. Conf. Recent Trends Electr. Control Commun., 2018, pp. 234-239.
[http://dx.doi.org/10.1109/RTECC.2018.8625691]
[6]
A. Hota, S. Jain, and V. Agarwal, "An improved three-phase five-level inverter topology with reduced number of switching power devices", IEEE Trans. Ind. Electron., vol. 65, pp. 3296-3305, 2018.
[http://dx.doi.org/10.1109/TIE.2017.2758722]
[7]
K.K. Gupta, A. Ranjan, P. Bhatnagar, L.K. Sahu, and S. Jain, "Multilevel inverter topologies with reduced device count: A review", IEEE Trans. Power Electron., vol. 31, pp. 135-151, 2016.
[http://dx.doi.org/10.1109/TPEL.2015.2405012]
[8]
M. Malinowski, K. Gopakumar, J. Rodriguez, and M.A. Pérez, "A survey on cascaded multilevel inverters", IEEE Trans. Ind. Electron., vol. 57, pp. 2197-2206, 2010.
[http://dx.doi.org/10.1109/TIE.2009.2030767]
[9]
M. Saeedian, E. Pouresmaeil, and E. Samadaei, "E. Manuel Godi-nho Rodrigues, R. Godina, and M. Marzband, “An innovative dual-boost nine-level inverter with low-voltage rating switches", Energies, vol. 12, p. 207, 2019.
[http://dx.doi.org/10.3390/en12020207]
[10]
V-T. Tran, M-K. Nguyen, C-C. Ngo, and Y-O. Choi, "Three-phase five-level cascade quasi-switched boost inverter", Electronics (Basel), vol. 8, p. 296, 2019.
[http://dx.doi.org/10.3390/electronics8030296]
[11]
A. Shojaei, B. Najafi, and H. Vahedi, "Standalone operation of Modified Seven-Level Packed U-Cell (MPUC) single-phase inverter", Electron, (Basel), vol. 8, p. 268, 2019.
[http://dx.doi.org/10.3390/electronics8030268]
[12]
V.-Q.-B. Ngo, M-K. Nguyen, T-T. Tran, J-H. Choi, and Y-C. Lim, "A modified model predictive power control for grid-connected T-type inverter with reduced computational complexity", Electron, (Basel), vol. 8, p. 217, 2019.
[http://dx.doi.org/10.3390/electronics8020217]
[13]
D. Karthikeyan, K. Vijayakumar, and J.M. Sathik, "Generalized cascaded symmetric and level doubling multilevel converter topology with reduced THD for photovoltaic applications", Electron. (Basel), vol. 8, no. 2, p. 161, 2019.
[http://dx.doi.org/10.3390/electronics8020161]
[14]
F.Z. Peng, "A generalized multilevel inverter topology with self-voltage balancing", IEEE Trans. Ind. Appl., vol. 37, pp. 611-618, 2001.
[http://dx.doi.org/10.1109/28.913728]
[15]
A. Nabae, I. Takahashi, and H. Akagi, "A new neutral-point-clamped PWM inverter", IEEE Trans. Ind. Appl., vol. IA-17, pp. 518-523, 1981.
[http://dx.doi.org/10.1109/TIA.1981.4503992]
[16]
T.A. Meynard, and H. Foch, "Multi-level conversion: high voltage choppers and voltage-source inverters", In: 23rd Annual IEEE Power Electronics Specialists Conference, vol. 28. 1977, pp. 397-403.
[17]
C. Dhanamjayulu, and S. Meikandasivam, "Implementation and comparison of symmetric and asymmetric multilevel inverters for dynamic loads", IEEE Access, vol. 6, pp. 738-746, 2018.
[http://dx.doi.org/10.1109/ACCESS.2017.2775203]
[18]
S.K. Chattopadhyay, and C. Chakraborty, "Performance of three-phase asymmetric cascaded bridge (16: 4: 1) multi-level inverter", IEEE Trans. Ind. Electron., vol. 62, pp. 5983-5992, 2015.
[http://dx.doi.org/10.1109/TIE.2015.2424191]
[19]
J. Kang, S. Hyun, J. Ha, and C. Won, "Improved neutral-point voltage-shifting strategy for power balancing in cascaded NPC/H-bridge inverter", Electronics (Basel), vol. 7, p. 167, 2018.
[http://dx.doi.org/10.3390/electronics7090167]
[20]
N. Sulake, A. Devarasetty Venkata, and S. Choppavarapu, "FPGA Implementation of a three-level boost converter-fed seven-level DC-link cascade H-bridge inverter for photo-voltaic applications", Electronics (Basel), vol. 7, p. 282, 2018.
[http://dx.doi.org/10.3390/electronics7110282]
[21]
M.M. Hasan, A. Abu-Siada, and M.S.A. Dahidah, "A three-phase symmetrical DC-Link multilevel inverter with reduced number of DC Sources", IEEE Trans. Power Electron., vol. 33, pp. 8331-8340, 2018.
[http://dx.doi.org/10.1109/TPEL.2017.2780849]
[22]
J. Ebrahimi, E. Babaei, and G.B. Gharehpetian, "A new multi-level converter topology with reduced number of power electronic components", IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 655-667, 2012.
[http://dx.doi.org/10.1109/TIE.2011.2151813]
[23]
E. Samadaei, S. Gholamian, and A. Sheikholeslami, "An envelope type (E-type) module: Asymmetric multilevel inverters with reduced components", IEEE Trans. Ind. Electron., vol. 63, no. 11, pp. 7148-7156, 2016.
[http://dx.doi.org/10.1109/TIE.2016.2520913]
[24]
E. Samadaei, A. Sheikholeslami, S.A. Gholamian, and J. Adabi, "A square T-Type (ST-Type) module for asymmetrical multilevel inverters", IEEE Trans. Power Electron., vol. 33, pp. 987-996, 2018.
[http://dx.doi.org/10.1109/TPEL.2017.2675381]
[25]
S. Ray, N. Gupta, and R.A. Gupta, "Prototype development and experimental investigation on cascaded five-level inverter based active filter for large-scale grid-tied photovoltaic", Int. J.Renew. Energ. Re-s., vol. 8, no. 3, 2018.
[26]
Y. Suresh, and A.K. Panda, "Research on a cascaded multi-level inverter by employing three phase transformers", IET Power Electron., vol. 5, no. 5, pp. 561-570, 2012.
[http://dx.doi.org/10.1049/iet-pel.2011.0150]
[27]
M.R.J. Oskuee, R.S. Varzeghan, and B.N. Khezerlu, "An efficient approach to reduce line voltage THD in a multilevel inverter with alterable DC sources", Recent Adv. Electr. Electron. Eng., vol. 8, no. 1, pp. 4-11, 2015.
[http://dx.doi.org/10.2174/2352096508666150309235836]
[28]
R. Kumar, and T. Deepa, "Line frequency sine modulation - a novel modulation scheme for multilevel inverters and its application towards enhanced illumination of incandescent bulb", Int. J. Power Electron., vol. 10, no. 4, 2019.
[http://dx.doi.org/10.1504/IJPELEC.2019.102504]
[29]
R. Kumar, and D. Thangavelusamy, "A modified nearest level modulation scheme for a symmetric cascaded H- bridge inverter", Gazi Uni. J. Sci., vol. 32, no. 2, pp. 471-481, 2019.
[30]
M.T. Khosroshahi, "Crisscross cascade multilevel inverter with reduction in number of components", IET Power Electron., vol. 7, no. 12, pp. 2914-2924, 2014.
[http://dx.doi.org/10.1049/iet-pel.2013.0541]
[31]
E. Babaei, S. Laali, and Z. Bayat, "A single-phase cascaded multilevel inverter based on a new basic unit with reduced number of power switches", IEEE Trans. Ind. Electron., vol. 62, no. 2, pp. 922-929, 2015.
[http://dx.doi.org/10.1109/TIE.2014.2336601]
[32]
E. Babaei, M.F. Kangarlu, and M. Sabahi, "Extended multi-level converters: An attempt to reduce the number of independent DC voltage sources in cascaded multilevel converters", IET Power Electron., vol. 7, no. 1, pp. 157-166, 2014.
[http://dx.doi.org/10.1049/iet-pel.2013.0057]
[33]
E. Babaei, "A cascade multilevel converter topology with reduced number of switches", IEEE Trans. Power Electron., vol. 23, pp. 2657-2664, 2008.
[http://dx.doi.org/10.1109/TPEL.2008.2005192]
[34]
Y. Hinago, and H. Koizumi, "A single-phase multilevel inverter using switched series/parallel DC voltage sources", IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2643-2650, 2010.
[http://dx.doi.org/10.1109/TIE.2009.2030204]
[35]
B. Mahato, S. Majumdar, and K. Jana, "Single‐phase modified T‐type-based multilevel inverter with reduced number of power electronic devices", Int. Transact. Electric. Energ. Syst., vol. 29, no. 11, 2019.
[http://dx.doi.org/10.1002/2050-7038.12097]
[36]
A. Alexander, and M. Thathan, "Modelling and analysis of modular multilevel converter for solar photovoltaic applica-tions to improve power quality", IET Renew. Power Gen., vol. 9, no. 1, pp. 78-88, 2015.
[http://dx.doi.org/10.1049/iet-rpg.2013.0365]
[37]
A. Nami, F. Zare, and A. Ghosh, "A hybrid cascade converter topology with series-connected symmetrical and asymmetrical diode-clamped H-bridge cells", IEEE Transact. Power Electron., vol. 26, no. 1, 2011.
[38]
A.D. Roy, and C. Umayal, "Performance analysis of a half bridge cell based asymmetrical multilevel inverter topology with minimum components", Rec. Adv. Electr. Electron. Eng., 2019.
[http://dx.doi.org/10.2174/2352096512666190417122807]
[39]
M. Handbook, "Reliability prediction of electronic equipment", MIL-HDBK, vol. 217F, p. 2, 1991.
[40]
K.B. Misra, Reliability analysis and prediction: A methodology oriented treatment Elsevier., vol. 15. 1st Ed 1992.
[41]
R. Allan, "A single-phase multilevel inverter using switched series/parallel DC voltage sources", IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2643-2650, 2013.

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